Failure rate prediction and prevention of die cracking in over molded plastic packages

Vijayakumar, Bhuvaneshwaran; Guo, Yifan

doi:10.1109/itherm.2006.1645429

Cited by 6 publications

(5 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[2,3] For this work, a 3D finite element model is established using ANSYS for the MAPBGA component to analyze the impact-induced stress and strain distribution within the silicon. Figure 7 is an overview of the implemented model.…”

Section: Finite Element Simulationmentioning

confidence: 99%

An evaluation of die crack risk of over-molded packages due to external impact

Khan

Ding³

2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Component failures due to physical damage to the silicon are occasionally observed on board assembly processes. Such failures typically are not detected until electrical testing is performed at the end of the process, making it challenging to identify where and how such damages could occur. While process steps are designed to apply the lowest force possible on components, excessive load can be introduced by unexpected events such as machine malfunction or accidental external impact. For over-molded packages, particularly for packages with a large die and thin mold cap thickness, protection for such abnormal impact is reduced and even low levels of force can induce damage to the silicon.In this work, impact test is performed on two types of over-molded packages that have different die and package geometries. External load is applied on the top of the packages through the drop of a probe from different heights. The damages induced in the silicon are evaluated with ultrasonic scan and cross-section. The results from these analytical steps will help identify the threshold force for the die crack failures. A finite element model is constructed to simulate the impact test for one of the packages. The time-history of the load is analyzed and the maximum stress levels in the silicon for the different drop heights are compared. Two different mold cap thicknesses are also simulated. By comparing the stress levels from the model and the real-life testing results, we are able to obtain general guidelines for the maximal impact allowed for the package investigated in this study and provide references for analysis of future failures.

show abstract

Section: Finite Element Simulationmentioning

confidence: 99%

An evaluation of die crack risk of over-molded packages due to external impact

Khan

Ding³

2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

show abstract

“…Thus, the reliability of electronics has become an important part of research and development. Hence, also rare failure mechanisms like chip fracture, have become more and more of interest [1][2][3] .…”

Section: Introductionmentioning

confidence: 99%

New equivalent stress describes the dicing caused anisotropic breaking strength of silicon dies

Steiert

Wilde

2014

2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and

View full text Add to dashboard Cite

Due to increased demands, reliability has become an important part of the research and development on electronics, in the last years. An important reliability factor is failure due to chip fracture. Tn several scientific papers three types of chip fracture are described: vertical cracks, horizontal cracks and mixed cracks. Till now, all approaches to explain the relations of these crack types have based on the deterministic fracture mechanics. But especially for statistical process control, it is better to use a probabilistic fracture mechanic based on the Weibull distribution.In the present work damages caused by the dicing were analyzed by means of SE M-pictures. A special type of crack was found. Such cracks have a preferred orientation which is parallel to the dicing feet direction. The influence of those cracks on the breaking strength of silicon chips was investigated. The results showed a kind of dicing caused anisotropic breaking strength. This means the fracture relevant die strength depends on the local orientation of the stresses which acts on the chips. To detail this phenomenon a new equivalent stress was develop, which offers to directly compare stresses by means of theirs impact to fracture.

show abstract

“…Because of ever increasing electronic applications especially in safety-relevant systems e.g. for automotive electronic stability control, also rare failure mechanisms like chip fracture, have become more and more of interest [1][2][3]. The chip fracture is essentially determined by two primary parameters.…”

Section: Introductionmentioning

confidence: 99%

“…For instance, Fig.1 shows stress sensor chips prepared for in situ analysis during the die attachment process [4]. An overview of previous investigations revealed typical silicon die stresses in the range of ±50 MPa up to ±200 MPa [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Chip-side-healing as a basis for robust bare-chip assemblies

Steiert

Wilde

2013

2013 IEEE 63rd Electronic Components and Technology Conference

View full text Add to dashboard Cite

During their life cycles, semiconductor devices are exposed to different mechanical loads as a result of assembly and packaging processes as well as by stresses due to environmental conditions during operation. Especially, in modern applications like high temperature sensors the diestrength and the fracture resistance of the used semiconductor are important factors for the system reliability. They often develop high stresses in the chips.The die-strength is considerably influenced by the wafer dicing because of process-induced damages, which are generated at the side walls of chips. Chip-side-healing (CSH) is a term for the selective removal of dicing damages with the aim to increase the die-strength. In this work, two new CSHprocesses are evaluated. The first one uses xenon difluoride (XeF 2 ) as the etching medium and the second process works with fluorine radicals to remove the damages.Both processes can remove all of the dicing damages. After the CSH the bending strength was nearly four times higher than without the aforementioned processes. In comparison to six common dicing techniques, diamondscribing, water-jet-laser-dicing, stealth-dicing, blade-dicing, deep-reactive-ion-etching and thermal-laser-separation, CSH shows better potential to increase the thermal-mechanical reliability of semiconductors.

show abstract

Failure rate prediction and prevention of die cracking in over molded plastic packages

Cited by 6 publications

References 6 publications

An evaluation of die crack risk of over-molded packages due to external impact

An evaluation of die crack risk of over-molded packages due to external impact

New equivalent stress describes the dicing caused anisotropic breaking strength of silicon dies

Chip-side-healing as a basis for robust bare-chip assemblies

Contact Info

Product

Resources

About