Failure diagnosis of structured VLSI

Waicukauski, J.A.; Lindbloom, Eric

doi:10.1109/54.32421

Cited by 254 publications

(72 citation statements)

References 6 publications

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“…It is critical to silicon debugging, yield analysis and for improving subsequent manufacturing cycle [6]- [8]. Recent research has reported a number of DFT solutions to test power-switches when considering the two possible type of faults: stuck-open and stuck-short [5], [9]- [11].…”

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confidence: 99%

Delay Test for Diagnosis of Power Switches

Khursheed

Shi

Al-Hashimi

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations.Index Terms-Sleep transistor, diagnosis, power gating, leakage power management, design for test (DFT).

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confidence: 99%

Delay Test for Diagnosis of Power Switches

Khursheed

Shi

Al-Hashimi

et al. 2014

IEEE Trans. VLSI Syst.

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“…Fault location may be required to identify and then replace the faulty subcircuit, or to analyze the defect causing the faulty behavior. The problem of fault location has been considered extensively (e.g., [1][2][3][4][5][6][7][8][9][10][11]). A broad class of fault location procedures rely on comparison of the circuit response with a set of responses produced by the circuit-under-test in the presence of modeled faults.…”

Section: Introductionmentioning

confidence: 99%

On improving fault diagnosis for synchronous sequential circuits

Pomeranz

Reddy

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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The multiple observation times approach was proposed as a test generation approach for fault detection, and was shown to alleviate deficiencies of conventional test generators. In this work, the multiple observation times approach is applied to fault location. It is shown that the use of multiple observation times has the potential of significantly enhancing the resolution of a given test set. A definition of pass/fail diagnosis suitable for the multiple observation times approach is also given. Experimental results are provided to demonstrate the approach and its advantages.

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“…The primary data recovery scheme presented in section 3.1 differs from the diagnosis scheme in [19,20] …”

Section: Alternative Data Recovery Schernesmentioning

confidence: 99%

“…(1 from the CUT, whereas the data retrieval met hod in [20] would transfer 512 I i b -r e s of data. an 8-fold saving.…”

Section: Dynamicarray Templatementioning

confidence: 99%