Failure Analysis of 1200-V/150-A SiC &lt;sc&gt;MOSFET&lt;/sc&gt; Under Repetitive Pulsed Overcurrent Conditions

Schrock, James A.; Pushpakaran, Bejoy N.; Bilbao, Argenis; Ray, William B.; Hirsch, E. A.; Kelley, Mitchell D.; Holt, S.; Bayne, Stephen

doi:10.1109/tpel.2015.2464780

Cited by 83 publications

(12 citation statements)

References 28 publications

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“…Recently, it has been discussed that robust short-circuit devices can be designed if the thickness of the oxide is increased or the cell pitch is increased, while on the other hand, the on-state resistance becomes compromised leading to greater power losses [17], [18]. Despite of this tradeoff curve, cracks across the thin gate-oxide have not been reported in the literature, as discussed in [19], therefore this assumption needs to be further validated. The aim of this paper is to perform failure analysis on 1.2-kV planar SiC MOSFETs, which have been degraded under This paper is organized as follows: Section II presents the results from the experimental short-circuit tests at different DC-link voltages and initial junction temperatures.…”

Section: Introductionmentioning

confidence: 99%

Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

Reigosa

Iannuzzo

Ceccarelli

2018

Microelectronics Reliability

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This paper presents the impact of a short-circuit event on the gate reliability in planar SiC MOSFETs, which becomes more critical with increased junction temperature and higher bias voltages. The electrical waveforms indicate that a gate degradation mechanism takes place, showing a large gate leakage current that increases as the gate degrades more and more. A failure analysis has been performed on the degraded SiC MOSFET and then compared to the structure of a new device to identify possible defects/abnormalities. A Focused Ion Beam cut is performed showing a number of differences in comparison to the new device: (i) cracks between the poly-silicon gate and aluminium source, (ii) metal particles near the source contact, and (iii) alterations in the top surface of the aluminium source. The defects have been correlated with the increase in gate-leakage current and drain-leakage current.

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Section: Introductionmentioning

confidence: 99%

Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

Reigosa

Iannuzzo

Ceccarelli

2018

Microelectronics Reliability

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“…The reported results showed 59 the weakness of the gate during SC tests and at different 60 failure modes. Experiments on SiC power MOSFET and 61 JFET were carried out in [20] under SC fault condition. 62 The device temperature was also estimated to be very high, 63 leading to melting of aluminum and finally to device failure.…”

mentioning

confidence: 99%

A Comprehensive Study of Short-Circuit Ruggedness of Silicon Carbide Power MOSFETs

Romano

Fayyaz

Riccio

et al. 2016

IEEE J. Emerg. Sel. Topics Power Electron.

205

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A note on versions:The version presented here may differ from the published version or from the version of record. If you wish to cite this item you are advised to consult the publisher's version. Please see the repository url above for details on accessing the published version and note that access may require a subscription.For more information, please contact eprints@nottingham.ac.uk I E E E P r o o f IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 1A

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“…To confirm the above theories, physical inspection of damaged SiC MOSFETs has been performed recently, showing cracks in the field oxide between the gate poly-silicon and the source contact [3], and showing melted aluminium [11]. Nevertheless, no damage has been observed in the thin gate oxide as discussed in [12]. The weakness of the gate oxide has also been observed through power cycling tests as reported in [13] and [14], where a positive shift of the threshold voltage has been detected.…”

Section: Introductionmentioning

confidence: 83%

Failure Analysis of a Degraded 1.2 kV SiC MOSFET after Short Circuit at High Temperature

Reigosa

Iannuzzo

Ceccarelli

2018

2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150 • C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gatevoltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.

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Failure Analysis of 1200-V/150-A SiC <sc>MOSFET</sc> Under Repetitive Pulsed Overcurrent Conditions

Cited by 83 publications

References 28 publications

Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

A Comprehensive Study of Short-Circuit Ruggedness of Silicon Carbide Power MOSFETs

Failure Analysis of a Degraded 1.2 kV SiC MOSFET after Short Circuit at High Temperature

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