2009
DOI: 10.1109/ispsd.2009.5158042
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Fabrication of trench isolation and trench power MOSFETs in a smart power IC Technology with a single trench unit process

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Cited by 7 publications
(2 citation statements)
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“…The device used in the electro-thermal simulations is a low voltage n-channel power MOSFET featuring the trench technology designed by Infineon Technologies discussed in [7]. In this technology the trench is 4 lm deep, while the pitch of the elementary cell is 3.2 lm, hence the active area associated with a single cell is 10.24 lm 2 , i.e.…”
Section: Thermal Modeling Of the Epitaxial Layermentioning
confidence: 99%
“…The device used in the electro-thermal simulations is a low voltage n-channel power MOSFET featuring the trench technology designed by Infineon Technologies discussed in [7]. In this technology the trench is 4 lm deep, while the pitch of the elementary cell is 3.2 lm, hence the active area associated with a single cell is 10.24 lm 2 , i.e.…”
Section: Thermal Modeling Of the Epitaxial Layermentioning
confidence: 99%
“…Compared with PN junction isolation, deep trench structure on SOI substrate shows a lot of advantages, such as minimal space consumption, bi-directional isolation, lower leakage current, higher stopping latch-up performance and stronger temperature tolerance in smart power applications [1][2][3]. In recent years, the isolation characteristics of deep trench have been published in many literatures.…”
Section: Introductionmentioning
confidence: 99%