Fabrication of three-dimensional IC using `cumulatively bonded IC' (CUBIC) technology

Hayashi, Y.; Wada, S.; Kajiyana, K.; Oyama, Koki; Koh, Risho; Takahashi, Shuji; Kunio, Takeshi

doi:10.1109/vlsit.1990.111025

Cited by 22 publications

(6 citation statements)

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“…5-10. Diese Performancedaten sind allerdings noch deutlich nach oben zu korrigieren, wenn bei der Potentialabschätzung SOI (Silicon On Insulator) und CUBIC (Cumulatively Bonded Integrated Circuits) [14] Techniken herangezogen werden, mit denen 3-dimensionale integrierte Schaltungen ähnlich wie bei "biologischen Systemen" hergestellt werden können. Allerdings sind zur Realisierung dieser Systeme noch wesentliche Fortschritte bei den Designsystemen und den "Packaging-Systemen" notwendig, bei denen die derzeitigen Trends (Bild 14) eher auf eine Konfliktsituation hinzeigen, die allerdings sowohl durch neuartige Packaging-Module (Multi Chip Module) als auch durch den verstärkten Trend zu "Systems On Chips" entschärft werden wird.…”

Section: Harmonisierungunclassified

„Systems on Chips": Die Herausforderung der nächsten 20 Jahre/ "Systems on Chips": The Microelectronic Challenge of the Next 20 Years

Wieder¹

1992

it - Information Technology

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Selbst bei unveränderter Fortschrittsgeschwindigkeit sind die Weiterentwicklungsperspektiven der Mikroelektronik über das Jahr 2010 hinaus nicht durch physikalisch-technologische Begrenzungen eingeengt.Für die anwendungsspezifischen Chancen und Entwicklungsperspektiven lassen sich ähnlich positive Aussagen formulieren: Selbst wenn man sich auf bereits heute schon im Prinzip verifizierte Strukturen beschränkt, läßt sich die Chip-Rechenleistung gegenüber heutigen Werten um ca. 4 Größenordnungen auf ca. 10 s -10 6 MIPS steigern. Allerdings ist dazu die Beachtung der im einzelnen dargestellten Maßnahmen im technologischen, schaltungstechnischen, designtechnischen und architektonischen Bereich notwendig.Neben der Weiterentwicklung der klassischen Märkte for Logik-ICs und Speicher-ICs, die auch weiterhin mit einem Wachstum von 10%-15% p.a. prognostiziert werden, werden zunehmend künden-und anwendungsspezifische Speicher mit On-Chip Logikanteilen Bedeutung bekommen. Das gilt auch für mit Speichern (nicht flüchtigen und flüchtigen) angereicherte Logikbausteine, die die Herstellung von neuartigen, in Analogie zu "biologischen Lösungen" hochverdrahteten Architekturen gestatten. Diese in CMOS/BICMOS-Technologie hergestellten "Systems on Chips" werden mit ihrem hohen operativen Autarkiegehalt wesentliches System-Knowhow heutiger Systeme enthalten und so zu den Modulen zukünftiger "Hy per-Syst eine" werden.Beyond the year 2010 the perspectives of microelectronics are not narrowed by technical limitations, even if progress advances as fast as in the past.Likewise positive statements can be formulated for application-perspectives. The chipcomputational power f.i. can be boosted by about 4 orders of magnitudes to 10 5 -10 6 MIPS. This implies, however, the consideration of various technological, circuit design, layout and architectural recommendations given in the paper.Conventional stand alone markets for memory and logic ICs are prognosted to grow by 10-15% per year for the next decade. User specific memories as well as logic with on-chip memories (volatile and non volatile), however, will become more and more important. These novel "systems on chips" will eliminate the limiting bottle neck of the on-chip/off-chip metallization. By that the technical approximation of "biological systems" will become feasible with system performance increased by orders of magnitudes. These systems on chips, which essentially contain todays system know how will become the modules of the "hypersystems" of tomorrow.

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Section: Harmonisierungunclassified

„Systems on Chips": Die Herausforderung der nächsten 20 Jahre/ "Systems on Chips": The Microelectronic Challenge of the Next 20 Years

Wieder¹

1992

it - Information Technology

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“…Semiconductor devices and computer systems have evolved as feature sizes have been continuously reduced [1][2][3][4]. On the other hand, three-dimensional technology has been considered since the 1980s, mainly from the viewpoint of monolithic ICs [5][6][7][8][9][10][11]. From the late 1990s, 3D technology has been widely studied for the hybrid structure, including package from the die-level to wafer-level, e.g., how to stack semiconductor elements and how to connect between stacked dies with the vertical interconnects such as TSVs [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27].…”

Section: Introductionmentioning

confidence: 99%

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

et al. 2022

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Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects between wafers and between chips and wafers are a second-generation alternative to the use of micro-bumps for WOW and COW technologies. WOW and COW technologies for BBCube can be used for homogeneous and heterogeneous 3DI, respectively. Ultra-thinning of wafers down to 4 μm offers the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Bumpless interconnect technology can increase the number of TSVs per chip due to the finer TSV pitch and the lower impedance of bumpless TSV interconnects. In addition, high-density TSV interconnects with a short length provide the highest thermal dissipation from high-temperature devices such as CPUs and GPUs. This paper describes the process platform for BBCube WOW and COW technologies and BBCube DRAMs with high speed and low IO buffer power by enhancing parallelism and increasing yield by using a vertically replaceable memory block architecture, and also presents a comparison of thermal characteristics in 3D structures constructed with micro-bumps and BBCube.

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“…In view of the aforementioned disadvantages of monolithic approach, alternative wafer bonding based method was proposed to implement 3D integration. In 1990, a "Cumulatively bonded IC" (CUBIC) technology was proposed by NEC corporation as the first exemplary 3D integration technique through wafer bonding [33]. As shown in Fig.…”

Section: D Integration Through Wafer Bondingmentioning

confidence: 99%

“…They can generally be classified into two categories. One is direct wiring, of which the representatives are micro-bumps [33][34][35] and through silicon vias (TSVs) [36][37][38]. The other is contactless approaches, such as the optical [45-48, 50, 51] and capacitive/inductive coupling based [52] interconnections.…”

Section: Inter-layer Interconnectionmentioning

confidence: 99%

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Thermal management of 3D integrated circuits with microchannel-based liquid cooling

Qian¹

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Fabrication of three-dimensional IC using `cumulatively bonded IC' (CUBIC) technology

Cited by 22 publications

References 0 publications

„Systems on Chips": Die Herausforderung der nächsten 20 Jahre/ "Systems on Chips": The Microelectronic Challenge of the Next 20 Years

„Systems on Chips": Die Herausforderung der nächsten 20 Jahre/ "Systems on Chips": The Microelectronic Challenge of the Next 20 Years

Review of Bumpless Build Cube (BBCube) Using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI)

Thermal management of 3D integrated circuits with microchannel-based liquid cooling

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