Fabrication of Suspended Ge-rich Nanowires by Ge Enrichment Technique for Multi-channel Devices

Abstract

This paper presents a new top-down method to fabricate Ge-rich nanowires for multi-channel devices by Ge enrichment technology. 3 dimensional Ge nanowire stacks have been fabricated and characterized by SEM, TEM, EDX. Nanowires obtained are single crystalline with no crystalline defects observed on cross-sectional TEM pictures. The main advantage of this method is that the shape, the size and the concentration of Ge nanowires can be tuned by process parameters. Indeed, depending on these parameters, nanowires with a Ge content up to 100% can be obtained with a very aggressive diameter (as low as 10nm). Moreover, this technology allows the co-integration of Ge and Si nanowires for pMOS and nMOS devices, respectively.

Electrical Transport at Room and Low Temperature in 3D Vertically Stacked SiGe and SiGeC Nanowires

“…An innovative fabrication process has been proposed based on the germanium condensation technique in silicon on insulator (SOI) layers. 8,9 The use of both selective etching of Si versus Ge and condensation technique allows the 3D integration of SiGe and Ge 3D nanowires. Figure 1 shows the fabrication process of two suspended Ge nanowires starting from an SOI wafer.…”

Transport Properties of 3D Vertically Stacked SiGe and SiGeC Nanowires

“…The innovative fabrication process is based on the germanium condensation technique on silicon on insulator (SOI) (6) and is detailed elsewhere (7). Fabricated nanowire channels are suspended and surrounded by silicon dioxide.…”

Electrical Transport Properties of 3D Vertically Stacked p-MOS SiGe and SiGeC Nanowires

“…In this abstract, the electrical transport properties of p-channel MOS NW are presented. The innovative fabrication process is based on the germanium condensation technique (4) and is detailed elsewhere (5). Fabricated nanowire channels are suspended and surrounded by silicon dioxide.…”