Fabrication of single-crystalline insulator∕Si∕insulator nanostructures

Fissel, A.; Kühne, Dirk; Bugiel, E.; Osten, H. J.

doi:10.1116/1.2213266

Cited by 26 publications

(10 citation statements)

References 38 publications

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“…resonant tunnelling diode systems [77]) or even more revolutionary approaches based on the tremendous diversity of solid state phenomena encountered in complex oxide systems (electric field effects in correlated oxide systems [78], correlated electron physics in transition metal oxides [79], all-oxide electronics [80,81] etc. ).…”

Section: Contributed Articlementioning

confidence: 99%

Engineered Si wafers: On the role of oxide heterostructures as buffers for the integration of alternative semiconductors

Schroeder

Giussani

Dąbrowski

et al. 2009

Phys. Status Solidi (c)

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Engineered Si wafer systems present an important materials science approach to further improve the performance of Si‐based micro‐ and nanoelectronics. This is due to the potential to integrate alternative semiconductor layers on the mature Si wafer technology platform which are otherwise too expensive or even impossible to grow in bulk form in the required quality and quantity. Ge is attracting increasing research interest because it is for example a promising material for high mobility channel CMOS technologies as well as a mediator material to achieve the manufacturing of III‐V/Si hybrid devices. The integration of Ge on Si wafers is today either achieved by a combination of layer transfer and wafer bonding techniques or by a sequence of subsequent, epitaxial thin film deposition growth steps. In the latter case, the traditional approach to integrate Ge layers of low defect densities is given by the use of compositionally graded SiGe heterostructures. As this approach suffers however from required SiGe buffer thicknesses on the micrometer scale, making integrated circuit processing difficult, research on the development of innovative buffer heteroepitaxy approaches is intensively pursued. A new interesting class of buffer materials with a high degree of flexibility is given by oxide heterostructures. Using the integration of single crystalline Si and Ge on the Si(111) material platform via oxide heterostructures as an example, the flexibility of engineered oxide heterostructures to control important epitaxy parameters is demonstrated. In this study, epitaxial Si(111) and Ge(111) layers were grown on cubic Y2O3(111)/cubic Pr2O3(111)/Si(111) and Pr2O3(111)/Si(111) support systems, respectively. The structural properties of the Si‐on‐Insulator (SOI) and Ge‐on‐Insulator (GOI) heterostructures were characterized in detail by a combination of laboratory‐ and synchrotron‐based methods. As main result, both the epitaxial Si(111) and Ge(111) films were shown to be atomically smooth and single crystalline (i.e. free of stacking twins). Defect engineering approaches need to be applied in future to reduce stacking faults (e.g. microtwins) which are identified as the major defect mechanism in the epitaxial Si(111) and Ge(111) films. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Contributed Articlementioning

confidence: 99%

Engineered Si wafers: On the role of oxide heterostructures as buffers for the integration of alternative semiconductors

Schroeder

Giussani

Dąbrowski

et al. 2009

Phys. Status Solidi (c)

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“…A considerable asymmetry of the band offsets to silicon, however, might compromise this advantage, resulting in a clear imbalance toward hole conduction ͓valence band ͑VB͒ offset 4,8,9 of ⌬VB = 2.0-2.2 eV and conduction band ͑CB͒ offset of ⌬CB = 2.6-2.8 eV͔.…”

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confidence: 97%

Leakage Current Mechanisms in Epitaxial Gd[sub 2]O[sub 3] High-k Gate Dielectrics

Gottlob

Echtermeyer

Schmidt

et al. 2008

Electrochem. Solid-State Lett.

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We report on leakage current mechanisms in epitaxial gadolinium oxide ͑Gd 2 O 3 ͒ high-k gate dielectrics suitable for low standby power logic applications. The investigated p-type metal-oxide-semiconductor capacitors are gated with complementary-metaloxide-semiconductor-compatible fully silicided nickel silicide electrodes. The Gd 2 O 3 thickness is 5.9 nm corresponding to a capacitance equivalent oxide thickness of 1.8 nm. Poole-Frenkel conduction is identified as the main leakage mechanism with the high-frequency permittivity describing the dielectric response on the carriers. A trap level of ⌽ T = 1.2 eV is extracted. The resulting band diagram strongly suggests hole conduction to be dominant over electron conduction.The semiconductor industry has been driven for the past four decades by a continuous downscaling of transistor dimensions. Today, however, further scaling of the traditional silicon oxide-based gate dielectrics is questionable due to intolerable gate leakage current levels. 1 An era of "material limited device scaling" has therefore been proclaimed in the latest edition of the International Technology Roadmap for Semiconductors ͑ITRS͒. 2 A key task, according to the ITRS, is the identification of transistor gate stacks with high dielectric constant ͑high-k͒ insulators and metal electrodes.Hafnium-based high-k oxides are widely considered as the nextgeneration gate dielectrics. Even though they will be introduced into manufacturing in the near future, it seems likely that another group of high-k materials will be needed to scale complementary-metaloxide-semiconductor ͑CMOS͒ technology to its final limit. The group of rare-earth or lanthanide oxides is rated as the top contender for this "final" high-k material. 3,4 Among them, epitaxially grown oxides have shown high potential. 5-7 A distinct advantage is associated with their deposition method: molecular beam epitaxy ͑MBE͒ potentially allows interface engineering, with abrupt interfaces to the silicon substrate and perfect lattice matching.The large bandgap of gadolinium oxide 5 ͑Gd 2 O 3 ͒ of E g = 5.9 eV is favorable for low leakage currents. A considerable asymmetry of the band offsets to silicon, however, might compromise this advantage, resulting in a clear imbalance toward hole conduction ͓valence band ͑VB͒ offset 4,8,9 of ⌬VB = 2.0-2.2 eV and conduction band ͑CB͒ offset of ⌬CB = 2.6-2.8 eV͔.Fully silicided ͑FUSI͒ nickel silicide ͑NiSi͒ metal gates are receiving increased interest due to their general CMOS process compatibility and their potential for work function tuning. 10,11 In addition, NiSi electrodes have been shown to be thermally and chemically stable on epitaxial Gd 2 O 3 during silicidation. 12 In this letter, we investigate the gate leakage current mechanisms in MOS capacitors with the material combination of epitaxial Gd 2 O 3 high-k dielectrics and FUSI NiSi metal gate electrodes. While ultra thin layers with a capacitance equivalent thickness ͑CET͒ of 0.86 nm and potential for high-performance logic applications have been pre...

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“…We name the entire procedure as 'encapsulated solid phase epitaxy'. Using encapsulated solid phase epitaxy, we could able to form single crystalline Gd 2 O 3 /Si/Gd 2 O 3 stacks on Si(111) substrates with very sharp oxide-Si interfaces [7]. …”

Section: A Growth Of Si-quantum Dots and Quantum Wells Simentioning

confidence: 99%

“…The arrangement of Si atoms occurs in low energy configuration due to heterogeneous nucleation of crystalline Si on the underlying epi-Gd 2 O 3 during temperature ramp up process. The crystallization starts at down Si/Gd 2 O 3 interface and subsequently moves into the bulk of the QW[7]. The oxide/Si heterostructures exhibit A/B-orientation relationship where the interface is atomically flat and homogeneous.The crystalline quality of the Gd 2 O 3 /Si/Gd 2 O 3 stack was also characterized by XRD measurements, shown in figure 3.…”

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confidence: 97%

Si Nanostructures Embedded into Crystalline Rare Earth Oxide Matrix for Opto and Nano Electronic Devices

Osten¹,

Laha²,

Fissel³

2010

2010 Fourth International Conference on Quantum, Nano and Micro Technologies

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We describe a novel approach to grow Si nanostructures embedded into crystalline rare earth oxides using molecular beam epitaxy. By efficiently exploiting the growth kinetics during growth one could create nanostructures exhibiting various dimensions, ranging from three dimensionally confined quantum dots to the quantum wells, where the particles are confined in of the dimensions. The crystalline rare earth oxide that has been used in this study is epitaxial gadolinium oxide (Gd 2 O 3 ). The room temperature quantum confinement effects characterized by the strong intensity and narrow photoluminescence peak in an array of Si quantum dots embedded in Gd 2 O 3 , indicates high crystalline quality and narrow size distribution range of quantum dots. The Si quantum dots with dimension about 3-5nm exhibited quantum confinement, which was observed in the photoluminescence and photoionization studies. The embedded Si-nanoclusters exhibit excellent charge storage capacity with competent retention and endurance characteristics;, and demonstrate their potential in future nonvolatile memory devices.

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Fabrication of single-crystalline insulator∕Si∕insulator nanostructures

Cited by 26 publications

References 38 publications

Engineered Si wafers: On the role of oxide heterostructures as buffers for the integration of alternative semiconductors

Engineered Si wafers: On the role of oxide heterostructures as buffers for the integration of alternative semiconductors

Leakage Current Mechanisms in Epitaxial Gd[sub 2]O[sub 3] High-k Gate Dielectrics

Si Nanostructures Embedded into Crystalline Rare Earth Oxide Matrix for Opto and Nano Electronic Devices

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