2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03 2003
DOI: 10.1109/icasic.2003.1277465
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Fabrication of Si and SiGe vertical dual carrier field effect transistor and its SOI resistor load switching ASIC with effective channel length of 30nm

G.H. Li1,
Ronghua Yang2,
Zheng Tang3
et al.
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Cited by 6 publications
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References 5 publications
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Design theory and library development of vertical dual carrier field effect transistor ASIC and SOC on SiO/sub 2/ and insulating GaAs substrate with effective channel length of 5-30nm

Huang1,
Yang2,
Huang3
2003
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03
6
0
0
0
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Design theory and library development of vertical dual carrier field effect transistor ASIC and SOC on SiO/sub 2/ and insulating GaAs substrate with effective channel length of 5-30nm

Huang1,
Yang2,
Huang3
2003
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03
6
0
0
0
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Principle of operation and performance of 1.3 volt SOI resistor load vertical dual carrier field effect transistor flip flop fabricated for SRAM, FPGA and switching SOC with effective channel length of 30nm

Tang1,
Li2,
Yang3
et al. 2003
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03
3
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1
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Design theory and fabrication process integration of 32nm node Si, Ge and Si<inf>1-x</inf>Ge<inf>x</inf> vertical dual carrier field effect transistor SOC for switching and communication applications

Huang
1
,
Yang
2
,
Huang
3
et al. 2007
2007 7th International Conference on ASIC
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