Fabrication of Novel Si Double-Barrier Structures and Their Characteristics

Abstract

A novel Si (silicon)-based double-barrier structure (DBS) is newly proposed to study Si resonant tunneling devices. To form a thin Si single-crystal plate as a quantum well, anisotropic wet chemical etching and thermal oxidation are adopted. The DBS has a 43 nm-wide Si quantum well and 2.3 nm-thick SiO2 barriers. The electrical characteristic exhibits negative differential conductance (NDC).

Phonon-Limited Electron Mobility Behavior and Inherent Mobility Reduction Mechanism of Ultrathin Silicon-on-Insulator Layer with (111) Surface and Ultrathin Germanium-on-Insulator Layer with (001) Surface

“…18) In real devices, it is anticipated that surface-roughness scattering will strongly effect electron mobility; 9) however, advances in etching techniques will yield virtually flat surfaces in the future. 12,13,19) A related discussion is given in §3.3.…”

“…8) Although, so far, the Si(111) surface has not been well utilized because of its low mobility, the excellent chemical stability of the Si(111) surface should be noted because it simplifies the fabrication of thin Si devices. 12,13) Thus, the application of the Si(111) surface to a FinFET on a (011) substrate is not simply a theoretical discussion.…”

Wafer-scale fabrication of high-quality tunable gold nanogap arrays for surface-enhanced Raman scattering

“…Such etching combination has been reported and used to fabricate various Si-based structures. [18][19][20][21][22][23] Subsequent conformal deposition of a silicon nitride layer and a gold layer resulted in dense arrays of high-quality gold nanogaps over full wafer areas. The gap spacing can be tuned down to 10 nm at high uniformity by changing the Au layer thickness.…”

Fabrication of Si double barrier structure

“…So far, most devices have been fabricated by compound semiconductor materials such as GaAs/AlGaAs focused on arithmetic logic circuits. 10 For discrete energy states in the quantum well, separation of energy states (⌬E) between the lowest two subbands must be larger than thermal broadening of the quantum states ϳk B T. Thus, a quantum well width (W) of less than 100 nm is needed at a liquid He temperature. However, a method for fabrication of the Si resonant tunneling device has to be established.…”

“…[1][2][3][4] On the other hand, to overcome the functional limitation of the Si integrated devices, new devices, such as Si resonant tunneling devices, are required. 10 Also, flat and clean surfaces are needed to eliminate electron scattering at the boundaries between well and barriers, and to prevent further broadening of the quantum states. [5][6][7][8][9] In this article, we report a new fabrication method for a Si-based resonant tunneling device.…”