2010
DOI: 10.1116/1.3455498
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Fabrication of nanowires with high aspect ratios utilized by dry etching with SF6:C4F8 and self-limiting thermal oxidation on Si substrate

Abstract: Si-based nanowires with high aspect ratios have been fabricated using an inductively coupled plasma reactive ion etching ͑ICP-RIE͒ with a continuous processing gas mixture of fluorine-based SF 6 :C 4 F 8 combined with a thermal oxidation technique. The subsequent thermal oxidation further reduced the nanowire diameter utilizing the self-limiting oxidation effect below the lithographic dimensions. Transmission electron microscopy analysis of the completed nanostructures revealed the total oxide thickness and th… Show more

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Cited by 14 publications
(9 citation statements)
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“…The subsequent DRIE of silicon cavities to the depth of 5 μ m, 7 μ m, and 10 μ m, respectively, was performed in a Plasma-Therm Versaline Inductively Coupled Plasma (ICP) by continuous processing with a gas mixture of SF 6 /C 4 F 8 /Ar. This process results in an anisotropic profile, while avoids scalloped sidewalls 58. The residual photoresist was removed in commercial solvents (NMP@75 C and PRS@75 C), followed by Piranha (H 2 SO 4 :H 2 O 2 ) solution.…”
Section: Methodsmentioning
confidence: 99%
“…The subsequent DRIE of silicon cavities to the depth of 5 μ m, 7 μ m, and 10 μ m, respectively, was performed in a Plasma-Therm Versaline Inductively Coupled Plasma (ICP) by continuous processing with a gas mixture of SF 6 /C 4 F 8 /Ar. This process results in an anisotropic profile, while avoids scalloped sidewalls 58. The residual photoresist was removed in commercial solvents (NMP@75 C and PRS@75 C), followed by Piranha (H 2 SO 4 :H 2 O 2 ) solution.…”
Section: Methodsmentioning
confidence: 99%
“…Recently, there has been increasing interest in ZnO-based nanowire transistors fabricated by top-down approaches [ 17 - 19 ] as opposed to the more common bottom-up self-assembly approach [ 20 ]. The top-down approach involves material deposition and anisotropic plasma etching to create a nanowire.…”
Section: Introductionmentioning
confidence: 99%
“…We evidenced that the deepest energy level is the point defect level HB2/HC2, which was detected in BSi-NWs and in standard Bosch-processed silicon substrate. We associated it to the defect VH 2 detected in low-energy H-ion-implanted Si. , We found also two broadened lines, HB1 in dry etched Si and HC1 in BSi-NWs, differing in activation enthalpy, capture cross section, and density. The zero-barrier analysis was successfully applied to fit both of the lines HB1 and HC1, allowing an assessment of their broadening quantitatively.…”
Section: Discussionmentioning
confidence: 85%
“…Literature reports that the damage induced by RIE varies with the depth from the processed surface (Figure S1 in the SI). Thus, to compare the generation of deep levels during the BSi-NWs fabrication with the case when their growth was inhibited, the same region had to be probed by DLTS in samples B and C. To this aim, preliminary capacitance–voltage measurements were performed and the depletion depths versus applied voltages were plotted (Figure S4 in the SI).…”
Section: Resultsmentioning
confidence: 99%