2015
DOI: 10.1007/s00542-015-2661-x
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Fabrication of high aspect ratio silicon micro-structures based on aluminum mask patterned by IBE and RIE processing

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Cited by 14 publications
(6 citation statements)
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“…Previous studies have also focused on high-aspectratio etching for micromechanical devices. Notable findings include a 5-mm-wide and 115-mm-deep trench (aspect ratio up to 23) in Zhou's 20 study, a 7-mm-wide and 160-mm-deep trench (aspect ratio up to 22.8) in Mu's 21 study, and a 5-mm-wide and 144.2-mm-deep trench (aspect ratio up to 28.8) in Hu's 22 study. Figure 19 shows a comparable series of trenches of 12 mm in width and 377 mm in depth (aspect ratio up to 31.4), with a sidewall angle of 89°, which reaches the highest aspect ratio and the deepest etching.…”
Section: Experiential Function Formulamentioning
confidence: 95%
“…Previous studies have also focused on high-aspectratio etching for micromechanical devices. Notable findings include a 5-mm-wide and 115-mm-deep trench (aspect ratio up to 23) in Zhou's 20 study, a 7-mm-wide and 160-mm-deep trench (aspect ratio up to 22.8) in Mu's 21 study, and a 5-mm-wide and 144.2-mm-deep trench (aspect ratio up to 28.8) in Hu's 22 study. Figure 19 shows a comparable series of trenches of 12 mm in width and 377 mm in depth (aspect ratio up to 31.4), with a sidewall angle of 89°, which reaches the highest aspect ratio and the deepest etching.…”
Section: Experiential Function Formulamentioning
confidence: 95%
“…Figure 3a-c shows the topographies of Al 2 O 3 , TiO 2 , and HfO 2 film with a thickness of 25 nm-based MIM capacitors. The analysis result reflects that the root-mean-square (Rq) roughness values of these three materials are only 2.18 nm, 2.57 nm, and 2.22 nm, which can indirectly depict the special surface area [32][33][34]. It was noticed that there are certain white "defects" in the film itself after ALD deposition, and these white "defects" actually refer to the peaks of the surface undulation of the dielectric layer.…”
Section: Resultsmentioning
confidence: 94%
“…Firstly, the wafer is etched by the deep reactive ion etching process into micro-trench arrays with a width of 6 μm and a depth of 160 μm as shown in Figure 1a. The capacitors are formed on high aspect ratio micro-trench structures that we have previously reported [22]. Then, 300 nm SiO 2 is grown by dry oxidation as an isolation layer to avoid the premature breakdown of the MIM capacitors due to the rough sidewall surface of the trenches.…”
Section: Methodsmentioning
confidence: 99%