Fabrication of 3.1kV/10A 4H-SiC Junction Barrier Schottky Diodes

Wang, Chengsen; Yuan, Hao; Song, Qi; Tang, Xiaoyan; Jia, Renxu; Zhang, Yuming; Zhang, Yimen; Yi-dong, Shen

doi:10.1109/asicon.2015.7517153

Cited by 2 publications

(1 citation statement)

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“…Finally, the main P+ region is formed using ion implantation with high doses, as shown in Figure 2d. All annealing conditions are implemented at the temperature of 1650 °C under argon ambient with the graphite cap [30]. This process is easier to implement than etching, and it avoids the extra interface charges caused by filling the dielectric after etching.…”

Section: Methodsmentioning

confidence: 99%

Step-Double-Zone-JTE for SiC Devices with Increased Tolerance to JTE Dose and Surface Charges

et al. 2018

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In this paper, an edge termination structure, referred to as step-double-zone junction termination extension (Step-DZ-JTE), is proposed. Step-DZ-JTE further improves the distribution of the electric field (EF) by its own step shape. Step-DZ-JTE and other termination structures are investigated for comparison using numerical simulations. Step-DZ-JTE greatly reduces the sensitivity of breakdown voltage (BV) and surface charges (SC). For a 30-μm thick epi-layer, the optimized Step-DZ-JTE shows 90% of the theoretical BV with a wide tolerance of 12.2 × 1012 cm−2 to the JTE dose and 85% of the theoretical BV with an improved tolerance of 3.7 × 1012 cm−2 to the positive SC are obtained. Furthermore, when combined with the field plate technique, the performance of the Step-DZ-JTE is further improved.

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Section: Methodsmentioning

confidence: 99%