Fabrication, electrical characterization and device simulation of vertical P3HT field-effect transistors

Xu, Bojian; Doǧan, Tamer; Wilbers, Janine G. E.; Jong, M. P. de; Bobbert, Peter A.; Wiel, Wilfred G. van der

doi:10.1016/j.jsamd.2017.11.003

Cited by 9 publications

(5 citation statements)

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“…A vertical geometry allows reduced area requirements by employing a submicrometer thick organic film as the transistor channel. [11,15] In order to fabricate the nanopillars with a high areal density (≈10 6 pillars mm −2 ), optical resist dots (100 nm radius) arranged in a hexagonal lattice (250 nm lattice constant) are created using displacement Talbot lithography (DTL). [13][14][15] This phenomenon is known as the shortchannel effect and it restricts further improvement of vertical OFETs (VOFETs).…”

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confidence: 99%

“…[7][8][9][10] From the architectural perspective, in an integrated pixelated device, transistors should also have small footprints so that light-emitting/-sensing devices can occupy larger areas on each pixel. [13][14][15] This phenomenon is known as the shortchannel effect and it restricts further improvement of vertical OFETs (VOFETs). A vertical geometry allows reduced area requirements by employing a submicrometer thick organic film as the transistor channel.…”

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confidence: 99%

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Short‐Channel Vertical Organic Field‐Effect Transistors with High On/Off Ratios

Doǧan

Verbeek

Kronemeijer

et al. 2019

Adv Elect Materials

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requires a large transistor width and a short transistor channel length in order to excel in the mentioned attributes. [7][8][9][10] From the architectural perspective, in an integrated pixelated device, transistors should also have small footprints so that light-emitting/-sensing devices can occupy larger areas on each pixel. Yet for planar OFETs, the device area increases with the width and decreasing the channel length demands high-resolution patterning. A vertical geometry allows reduced area requirements by employing a submicrometer thick organic film as the transistor channel. [11,12] However, when the channel length of an OFET approaches the 100 nm regime, high electric fields result in large bulk current densities that cannot be modulated efficiently via a gate-field. [13][14][15] This phenomenon is known as the shortchannel effect and it restricts further improvement of vertical OFETs (VOFETs).In this report, a novel VOFET geometry is demonstrated addressing the short-channel effect, in particular by suppressing the undesired bulk current. It is based on a gate electrode consisting of massively parallel highly doped silicon nanopillars (Figure 1). Crucially different from other VOFETs, an insulating layer is deposited on top of the bottom contact in order to force injection of the charge carriers only from the sides of the bottom metal, and current flow within a thin layer close to the gate dielectric, minimizing space-charge limited current through the bulk semiconductor. Thanks to this unique geometry, ON/OFF ratios up to 10 6 can be realized, i.e., at least three orders of magnitude larger than in previously reported short-channel (100 nm) VOFETs. [11,15] In order to fabricate the nanopillars with a high areal density (≈10 6 pillars mm −2 ), optical resist dots (100 nm radius) arranged in a hexagonal lattice (250 nm lattice constant) are created using displacement Talbot lithography (DTL). It allows for fast wafer-scale patterning. [16] This resist dot pattern acts as an etch mask during etching of about 300 nm into the underlying silicon. Since the silicon is highly doped p-type (resistivity of 0.010-0.025 Ω cm), it can be directly used as a massively parallel nanopillar gate electrode for a single device (≈7 × 10 5 pillars per device of total size 0.7 µm 2 ). In our experiments, we use bulk silicon wafers, but silicon-on-insulator wafers can be used in order to electrically separate individual many-pillar devices. A stoichiometric low-pressure chemical-vapor-deposited (LPCVD) 45 nm silicon nitride (Si 3 N 4 ) isolates these A unique vertical organic field-effect transistor structure in which highly doped silicon nanopillars are utilized as a gate electrode is demonstrated. An additional dielectric layer, partly covering the source, suppresses bulk conduction and lowers the OFF current. Using a semiconducting polymer as active channel material, short-channel (100 nm) transistors with ON/OFF current ratios up to 10 6 are realized. The electronic behavior is explained using space-charge and contact-lim...

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confidence: 99%

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confidence: 99%

Short‐Channel Vertical Organic Field‐Effect Transistors with High On/Off Ratios

Doǧan

Verbeek

Kronemeijer

et al. 2019

Adv Elect Materials

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“…Therefore, our synthesized PI layers have good insulating properties and suitable characteristics for gate dielectrics of OFETs or integrated circuits. Generally, the morphology of organic semiconducting layers deposited on the polymeric layers (PI layers in our work) is a significant factor in configured device applications, because charge-carrier transport in OFETs with bottom-gate top-contact configuration mainly occurs in a few-nanometers-wide channel at the interface between organic semiconductors and gate dielectrics [22]. Indeed, the crystalline morphology of the active layers (organic semiconducting layers), which are determined by the surface properties of the gate dielectric layer (surface energy, surface roughness, and chemical functionality), strongly affect the electrical performance of OFETs [23,24].…”

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confidence: 99%

Mass-Synthesized Solution-Processable Polyimide Gate Dielectrics for Electrically Stable Operating OFETs and Integrated Circuits

et al. 2021

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Polyimides (PIs) are widely utilized polymeric materials for high-temperature plastics, adhesives, dielectrics, nonlinear optical materials, flexible hard-coating films, and substrates for flexible electronics. PIs can be facilely mass-produced through factory methods, so the industrial application value is limitless. Herein, we synthesized a typical poly(amic acid) (PAA) precursor-based solution through an industrialized reactor for mass production and applied the prepared solution to form thin films of PI using thermal imidization. The deposited PI thin films were successfully applied as gate dielectrics for organic field-effect transistors (OFETs). The PI layers showed suitable characteristics for dielectrics, such as a smooth surface, low leakage current density, uniform dielectric constant (k) values regardless of frequency, and compatibility with organic semiconductors. Utilizing this PI layer, we were able to fabricate electrically stable operated OFETs, which exhibited a threshold voltage shift lower than 1 V under bias-stress conditions and a field-effect mobility of 4.29 cm2 V−1 s−1. Moreover, integrated logic gates were manufactured using these well-operated OFETs and displayed suitable operation behavior.

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“…As shown in our previous work [1], V th =-0.8 V for device A′ at V DS =-3 V, but V th =-1 V for device A at V DS =-3 V. Again, such an obvious change provides another evidence to approve our above supposal: contact resistance at the interfaces of Al inter-gate electrode and at the two electrodes reduce after storing the device A for a long-enough time. The operation mechanism of the vertical organic transistors, including organic FETs [23,24] and space-charge-limited transistors [25], was described by SCLC theory under applied biases.…”

Section: Transport and Operation Mechanismmentioning

confidence: 99%

Influence of contact resistance on the electrical characteristics of organic static induction transistors

Zhang

Yang

Jiang

et al. 2019

Semicond. Sci. Technol.

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The influencing factors on the current-voltage (I-V ) characteristics of organic static induction transistors (OSITs) are complicated and usually the underneath physical mechanism depends on many parameters. In this paper, firstly we come up with a typical OSIT model and summarize its theoretical equations to the I-V curves of pentacene-based OSIT ITO(Source)/Pentacene/ Al(Gate)/Pentacene/Au(Drain) under both negative drain-source voltage and gate voltage (V G ), and the influence of contact resistance on OSITs is investigated. Our simulation showed that the injection barriers, the depletion layer and the gate controlling reduce when OSIT approaches the space-charge-limited current mode by decreasing the negative V G , which confirms our previous supposal that the contact resistance at the interfaces of Al inter-gate electrode and at the two injection electrodes reduces after keeping the device for a long-enough time. Also, our simulating equations can be applied to other organic based OSITs under positive both V DS and V G .

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Fabrication, electrical characterization and device simulation of vertical P3HT field-effect transistors

Cited by 9 publications

References 53 publications

Short‐Channel Vertical Organic Field‐Effect Transistors with High On/Off Ratios

Short‐Channel Vertical Organic Field‐Effect Transistors with High On/Off Ratios

Mass-Synthesized Solution-Processable Polyimide Gate Dielectrics for Electrically Stable Operating OFETs and Integrated Circuits

Influence of contact resistance on the electrical characteristics of organic static induction transistors

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