Fabrication and electrical characterization of homo- and hetero-structure Si/SiGe nanowire Tunnel Field Effect Transistor grown by vapor–liquid–solid mechanism

Brouzet, V.; Salem, B.; Periwal, P.; Alcotte, Reynald; Chouchane, Fares; Bassani, F.; Baron, T.; Ghibaudo, G.

doi:10.1016/j.sse.2016.01.005

Cited by 16 publications

(6 citation statements)

References 19 publications

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“…Possible fabrication steps for the proposed MSH-DG-TFET are shown in Fig. 2, which are in accordance with previous literature [50][51][52][53][54][55]. In brief, p-i-n based source-channel-drain region could be formed on Si substrate \ 100 [ by utilizing ion implantation processes with the help of appropriate masking as depicted in Fig.…”

Section: Device Structure and Simulation Strategiessupporting

confidence: 66%

Impact of interfacial charges on analog and RF performance of Mg2Si source heterojunction double-gate tunnel field effect transistor

Dassi

Madan

Pandey

et al. 2021

J Mater Sci: Mater Electron

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Tunnel field effect transistors (TFETs) have proved themselves as a better choice for the replacement of MOSFET due to provision of scalability and possibility of better realization of goal to achieve subthreshold swing less than 60 mV/decade. Challenge of lower ON current in conventional TFET has been overcome by a heterojunction double-gate (DG) TFET structure in which a low bandgap material, magnesium silicide (Mg 2 Si) is implemented as source region. There is dire need to determine the reliability of such device under various constraints to optimize them for low-power and high-speed applications. Therefore, in this paper, authors examine the device reliability by investigating the analog/RF performance of Mg 2 Si source heterojunction double-gate TFET (MSH-DG-TFET) under the influence of interface trap charge polarity and density. This reliability analysis is accomplished by including the effect of trap charges (both positive interface charges, i.e., donors and negative interface charges, i.e., acceptors) at Si/SiO 2 interface. Presence of these trapped acceptor and donor charges at Si/ SiO 2 interface modifies the flat-band voltage which in turn alters the performance of the device. It is revealed that for positive trap charge density of 1 9 10 12 cm -2 , the leakage current or off-state current of MSH-DG-TFET drastically increases from an order of 10 -18 to 10 -14 A/lm, thus degrading the performance. Further, presence of negative trap charges at interface tends to enhance the flat-band voltage that translates to the higher gate bias to turn the device ON. Results reveal that impact of positive interface charges is more pernicious on the device performance as compared to the negative interface charges. Thus, MSH-DG-TFET is susceptible to the donor traps existing at Si/ SiO 2 in comparison with the acceptor traps. Studies carried out may prove to be very useful for future research work in suggesting better TFET structures comprising of Mg 2 Si as source.

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Section: Device Structure and Simulation Strategiessupporting

confidence: 66%

Impact of interfacial charges on analog and RF performance of Mg2Si source heterojunction double-gate tunnel field effect transistor

Dassi

Madan

Pandey

et al. 2021

J Mater Sci: Mater Electron

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“…There remains a need for semiconductor nanowire manufacturing processes that simultaneously offer scalability and nanoscale control of composition. Semiconductor nanowires are promising building blocks for future electronic, − photonic, , energy, , and biological − applications. The vapor–liquid–solid (VLS) mechanism is a workhorse tool in this regard, permitting the growth of nanowire heterostructures such as Si/SiGe, ,− InAs/InP, and GaS/GaP as well as superlattices of Si/SiGe and InAs/InP , by switching between precursors during growth.…”

Section: Introductionmentioning

confidence: 99%

“…Semiconductor nanowires are promising building blocks for future electronic, − photonic, , energy, , and biological − applications. The vapor–liquid–solid (VLS) mechanism is a workhorse tool in this regard, permitting the growth of nanowire heterostructures such as Si/SiGe, ,− InAs/InP, and GaS/GaP as well as superlattices of Si/SiGe and InAs/InP , by switching between precursors during growth. At the same time, most VLS growth occurs on flat substrates.…”

Section: Introductionmentioning

confidence: 99%

Programming Semiconductor Nanowire Composition with Sub-100 nm Resolution via the Geode Process

et al. 2022

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We demonstrate the vapor–liquid–solid growth of single-crystalline i-Si, i-Si/n-Si, and Si x Ge1–x /Si y Ge1–y nanowires via the Geode process. By enabling nanowire growth on the large internal surface area of a microcapsule powder, the Geode process improves the scalability of semiconductor nanowire manufacturing while maintaining nanoscale programmability. Here, we show that heat and mass transport limitations introduced by the microcapsule wall are negligible, enabling the same degree of compositional control for nanowires grown inside microcapsules and on conventional flat substrates. Efficient heat and mass transport also minimize the structural variations of nanowires grown in microcapsules with different diameters and wall thicknesses. Nanowires containing at least 16 segments and segment lengths below 75 nm are demonstrated.

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“…Furthermore, use of SiGe results in high-speed performance even at similar biasing circumstances like Si material. Owing to this, many works were reported for the improvement of tunneling probability in TFETs by varying different mole fractions (x) of Ge [12]- [15]. Above all, SiGe has shown the ability to replace silicon with simple CMOS processing steps rather going for aggressive processing steps like major compound semiconductors and 2D materials [16].…”

Section: Introductionmentioning

confidence: 99%

Influence of Fringing-Field on DC/AC Characteristics of Si₁₋ₓGeₓ Based Multi-Channel Tunnel FETs

Thoti

2020

IEEE Access

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Tunnel field-effect transistors (TFETs) are the decent performance estimators in the prospective of short-channel effects. In such structures, a small inter-gate separation (IGS) is a key factor that appraises for high packed-density with more number of channels (N ) to deliver superior performance. Hence, the investigation is majorly focused on scaling IGS and its fringing-field impact on device behavior for the first time. The outcomes reveal that the high fringing-field initiates for IGS < 10 nm and influences the tunneling probability and scattering strongly at 1-nm IGS, which affect the DC and RF characteristics; hence, optimized values of IGS are investigated and determined as IGS > 10 nm. The results state that the optimized IGS can provide source to deliver high ratio of on-and off-current (I on /I off ). Even though, a small IGS is beneficial for reduction in the total capacitance, the RF performance improvement depends on a large IGS. The investigation is further extended and quantified for the finest IGS in multi-channel TFETs when N varies from 1 to 10. These analyses are assessed for the emerging technological nodes.INDEX TERMS Band-to-band tunneling model, channel number (N ), fringing-field, inter-gate separation, multi-channel tunnel-field effect transistor, Si 1−x Ge x .

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Fabrication and electrical characterization of homo- and hetero-structure Si/SiGe nanowire Tunnel Field Effect Transistor grown by vapor–liquid–solid mechanism

Cited by 16 publications

References 19 publications

Impact of interfacial charges on analog and RF performance of Mg2Si source heterojunction double-gate tunnel field effect transistor

Impact of interfacial charges on analog and RF performance of Mg2Si source heterojunction double-gate tunnel field effect transistor

Programming Semiconductor Nanowire Composition with Sub-100 nm Resolution via the Geode Process

Influence of Fringing-Field on DC/AC Characteristics of Si₁₋ₓGeₓ Based Multi-Channel Tunnel FETs

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