Extreme wafer thinning optimization for via-last applications

Jourdain, Anne; Vos, Joeri De; Inoue, Fumihiro; Rebibis, Kenneth June; Miller, Andy; Beyer, Gerald; Beyne, Eric; Walsby, Edward; Patel, Jash; Ansell, Oliver; Hopkins, Janet; Ashraf, Huma; Thomas, Dave

doi:10.1109/3dic.2016.7970028

Cited by 14 publications

(3 citation statements)

References 1 publication

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“…Existing work looking at TSV reveal or smoothing processes using dry etch techniques have not specifically addressed the subject of post back-grind damage and the visibility of the grind-marks as a direct CMP replacement and report much longer smoothing times than the process described here [15,21,22], or looked at achieving smooth vertical sidewalls during TSV formation.…”

Section: Resultsmentioning

confidence: 99%

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A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

Mumford

Hopkins

Guy

2023

IEEE Trans. Semicond. Manufact.

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3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing.

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Section: Resultsmentioning

confidence: 99%

“…This reduces wafer loading and unloading steps, leading to cost and time savings. [15] [16]. The two processes combined take approximately ten minutes to complete from wafer loading to unloading for a typical TSV reveal.…”

Section: Tsv Reveal Processmentioning

confidence: 99%

A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

Mumford

Hopkins

Guy

2023

IEEE Trans. Semicond. Manufact.

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“…Three-dimensional System-On-Chip (3D-SoC) technology schemes require wafer-towafer bonding combined with good control of the Si thickness and the Si within wafer uniformity (1,2). As a result, there is a renewed interest in epitaxial strained Si1-xGex as etch stop layer (ESL) (3).…”

Section: Introductionmentioning

confidence: 99%

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

et al. 2020

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We describe challenges of the epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-capping, even for thinner Si0.75Ge0.25 layers. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap / Si0.75Ge0.25 // Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer to wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

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Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects

Vos

Peng

Phommahaxay

et al. 2016

2016 IEEE International 3D Systems Integration Conference (3DIC)

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Extreme wafer thinning optimization for via-last applications

Cited by 14 publications

References 1 publication

A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects

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