Extreme Software Defined Radio – GHz in Real Time

Abstract

Software defined radio is a widely accepted paradigm for design of reconfigurable modems. The continuing march of Moore's law makes real-time signal processing on general purpose processors feasible for a large set of waveforms. Data rates in the low Mbps can be processed on low-power ARM processors, and much higher data rates can be supported on large x86 processors.The advantages of all-software development (vs. FPGA/DSP/GPU) are compellingmuch wider pool of talent, lower development time and cost, and easier maintenance and porting. However, very high-rate systems (above 100 Mbps) are still firmly in the domain of custom and semi-custom hardware (mostly FPGAs). In this paper we describe an architecture and testbed for an SDR that can be easily scaled to support over 3 GHz of bandwidth and data rate up to 10 Gbps. The paper covers a novel technique to parallelize typically serial algorithms for phase and symbol tracking, followed by a discussion of data distribution for a massively parallel architecture. We provide a brief description of a mixed-signal front end and conclude with measurement results. To the best of the author's knowledge, the system described in this paper is an order of magnitude faster than any prior published result.

A DSEL for high throughput and low latency software‐defined radio on multicore CPUs

“…To create a socket, four parameters are required: its datatype (given as a template parameter), its associated task, its name, and its size. Finally, a "codelet" function need to be set (lines [14][15][16][17][18][19][20][21][22][23][24][25][26]. This codelet will be called when the task will be triggered.…”

A DSEL for High Throughput and Low Latency Software-Defined Radio on Multicore CPUs

“…• Grayver and Utter. In a recently published paper [18], they succeed in building a 10 Gb/s DVB-S2 receiver on a cluster of server-class CPUs. The implementation is closed sources, making fair comparisons difficult.…”

“…SDR can be implemented on various targets such as Field Programmable Gate Arrays (FPGAs) [7]- [12], Digital Signal Processors (DSPs) [10], [13], [14] or General Purpose Processors (GPPs) [15]- [18]. Many SDR elementary blocks have been optimized for Intel ® and ARM ® CPUs.…”

A Flexible and Portable Real-time DVB-S2 Transceiver using Multicore and SIMD CPUs

“…Grayver and Utter recently published a paper [2] in which they succeed to build a 10 Gb/s DVB-S2 receiver on a cluster of server-class CPUs. On a comparable CPU, their work is able to double or even triple the throughput of our implementation (approximately 185 Mb/s on 20 cores).…”

“…They are either flexibility oriented, as for example by using the GNU radio software suite [1], but at the expense of performance, not suitable with real time processing. On the other hand, highly optimized solutions exist, but they sacrifice flexibility [2]. Moreover, the code is not available, which limits its reusability and reproducibility.…”