A Flexible and Portable Real-time DVB-S2 Transceiver using Multicore and SIMD CPUs

Cassagne, Adrien; Léonardon, Mathieu; Tajan, Romain; Leroux, Camille; Jégo, Christophe; Aumage, Olivier; Barthou, Denis

doi:10.1109/istc49272.2021.9594063

Cited by 2 publications

(2 citation statements)

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“…This paper is an extension of a previous work 40 in which we presented a complete, real‐life example, digital communication system (a DVB‐S2 transceiver) running on both x86 (Intel® ) and ARM (Cavium® ) CPUs, that meets real‐time requirements for ground‐satellite transceivers. This paper includes the DVB‐S2 software transceiver as well as the following new contributions: A DSEL based on C++ to build parallel dataflow graphs for SDR signal processing, supporting loops (including nested and input‐dependent ones), conditionals, early exits, pipeline and fork/join parallelism; A set of micro‐benchmarks to analyze the time taken by the different constructs; In‐depth insights to understand the performance and the genericity of the proposed DVB‐S2 transceiver (for instance, two pipeline implementations are compared and its implementation with the proposed DSEL is shown); A comprehensive and “as fair as possible” comparison with State‐of‐the‐Art DVB‐S2 software transceivers. …”

Section: Introductionmentioning

confidence: 98%

“…For a SDR operating in antennas or transceivers, memory footprint is not an issue and all tasks run on CPU cores. This paper is an extension of a previous work 40 in which we presented a complete, real-life example, digital communication system (a DVB-S2 transceiver) running on both x86 (Intel® ) and ARM (Cavium® ) CPUs, that meets real-time requirements for ground-satellite transceivers. This paper includes the DVB-S2 software transceiver as well as the following new contributions:…”

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confidence: 99%

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A DSEL for high throughput and low latency software‐defined radio on multicore CPUs

Cassagne¹,

Tajan

Aumage

et al. 2023

Concurrency and Computation

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SummaryThis article presents a new Domain Specific Embedded Language (DSEL) dedicated to Software‐Defined Radio (SDR). From a set of carefully designed components, it enables to build efficient software digital communication systems, able to take advantage of the parallelism of modern processor architectures, in a straightforward and safe manner for the programmer. In particular, proposed DSEL enables the combination of pipelining and sequence duplication techniques to extract both temporal and spatial parallelism from digital communication systems. We leverage the DSEL capabilities on a real use case: a fully digital transceiver for the widely used DVB‐S2 standard designed entirely in software. Through evaluation, we show how proposed software DVB‐S2 transceiver is able to get the most from modern, high‐end multicore CPU targets.

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