Extreme Short-Channel Effect on RTS and Inverse Scaling Behavior: Source–Drain Implantation Effect in 25-nm nand Flash Memory

Kim, Tae-Hoon; Franklin, Nathan; Srinivasan, Charan; Kalavade, P.; Goda, Akira

doi:10.1109/led.2011.2159573

Cited by 15 publications

(12 citation statements)

References 9 publications

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“…Different values were found in NOR arrays, owing once more to differences in cell design and cycling conditions. Such dependences prompted several works and studies on the optimization of the cell process/architecture in order to reduce the extent of the RTN [124,[126][127][128][129][130][131][132][133][134]. In the NAND array, moreover, the RTN amplitude was shown to depend on the cell position and state along the string [135,136] (because of the different transconductances, depending on the source and drain series resistances) and on the state of cells on adjacent BLs [137] (because of the modification in the electron density profile induced by electrostatic interference).…”

Section: Main Experimental Datamentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Main Experimental Datamentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…However, the dimensions of the MOSFETs used in ULSI designs have been continuously reduced in order to achieve higher device/circuit density. Moreover, it is well known that the threshold voltage th of a small device will be different from that of a long or wide device due to a combination of the short-channel effect (SCE) [7][8][9], the narrow-width effect (NWE) [10,11], the reverse short-channel effect (RSCE) [12,13], and the reverse narrow-width effect (RNWE) [14,15]. Meanwhile, the equations of a MOSFET in HSpice are evolved from Level 1 (Shichman-Hodges model) to BSIM3 Level 49 [16][17][18].…”

Section: Introductionmentioning

confidence: 99%

TheI-VCharacteristic Prediction of BCD LV pMOSFET Devices Based on an ANFIS-Based Methodology

Chen

2015

Advances in Fuzzy Systems

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Comprehensive and predictive modeling of submicron devices using the traditional TCAD EDA tools of device simulation has become increasingly perplexing due to a lack of reliable models and difficulties in calibrating available device models. This paper proposes a new technique to model BCD submicron pMOSFET devices and to predict device behaviors under different bias conditions and different geometry dimensions by using the adaptive neurofuzzy inference system (ANFIS), which combines fuzzy theory and adaptive neuronetworking. Here, the power of using ANFIS to realize theI-Vbehaviors is demonstrated in these p-channel MOS transistors. After a systematic evaluation, it can be found that the predicting results ofI-Vbehaviors of complicated submicron pMOSFETs by ANFIS are compared with the actual diagnostic experiment data, and a good agreement has been obtained. Furthermore, the error percentage was no greater than 2.5%. As such, the demonstrated benefits of this new proposed technique include precise prediction and easier implementation.

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“…It is well known that omit to avoid program disturbance, the scaled cell gate length cannot increase the boron channel doping concentration. Correspondingly, the S/D doping must be reduced to suppress short channel effect (SCE) and program disturbance, [18][19][20][21][22] thus warranting a more thorough investigation of RTN for the cell with low or eliminated S/D doping levels. Even without S/D doping, fringing fields induced by neighboring floating gates (FGs) can produce an adequate number of surface electrons and achieve a sufficient string ON-current level.…”

Section: Introductionmentioning

confidence: 99%

“…Even without S/D doping, fringing fields induced by neighboring floating gates (FGs) can produce an adequate number of surface electrons and achieve a sufficient string ON-current level. [23][24][25][26] Several RTN-related studies involving SCE, S/D implantation, 18,21) channel doping, cell shape, [27][28][29] and adjacent cell interference have been performed recently. 30,31) Analyzing how RTN affects S/D regions is a priority concern owing to the reduction of S/D doping when the cell size is scaled down to sub-25 nm.…”

Section: Introductionmentioning

confidence: 99%

Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

Li¹,

Shirota²

2013

Jpn. J. Appl. Phys.

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A comprehensive numerical study of threshold voltage fluctuation (ΔV T) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space [source/drain (S/D)] region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of ΔV T is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (V pass) and the neighboring cell V T (V T(n)), owing to the fringing fields of neighboring floating gates (FGs). As a result, ΔV T increases in the S/D region as V pass - V T(n) decreases. The fluctuation amplitude strongly depends on the [single-trap RTN] position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high ΔV T area moves from the AA edge towards the center area along the W-direction.

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Extreme Short-Channel Effect on RTS and Inverse Scaling Behavior: Source–Drain Implantation Effect in 25-nm nand Flash Memory

Cited by 15 publications

References 9 publications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

TheI-VCharacteristic Prediction of BCD LV pMOSFET Devices Based on an ANFIS-Based Methodology

Impact of Source/Drain Junction and Cell Shape on Random Telegraph Noise in NAND Flash Memory

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