Extracting INT8 Multipliers from INT18 Multipliers

Abstract

With the advent of machine learning as perhaps the most high-profile application area for FPGAs, there is a compelling reason to improve the provision of smaller precision arithmetic on these devices. INT8 is commonly used for AI inferencing, and along with some additional soft logic for exponent handling, can be an effective solution for training as well. This paper describes techniques for efficiently extracting INT8 multipliers from commonly available INT18 multipliers found in many modern FPGAs. A small amount of soft logic -as little as 7 ALMs per INT8 multiplier -is required to provide pre or post multiplier correction to calculate two INT8 multiplies from a single 18x18 multiplier. We present two configurations for both signed and unsigned representations where two multiplications share one input operand. In addition to the individual INT8 variants, we present full device cases of 22,400 INT8 multipliers organized as DOT32 product arrays, with the soft logic tightly bound to the INT18 based DSP Blocks. A majority of the soft logic and routing in the device is left untouched, and available for application development.

Optimizing Reconfigurable Recurrent Neural Networks

“…[19] showed methods to extract two INT8 multipliers from Xilinx DSP48E2 Blocks which contain a 27x18 multiplier. [20] illustrated a method to pack 2 INT8 multiplications into one INT18 multiplier with extra ALMs. Both these methods require two multiplications to share one input operand.…”

“…With our column-wise MVM using in RNN designs, one column of the weights matrix naturally shares the same element of the input vector and conducts the multiplications at the same time. Thus, these multiplications share one input operand, which helps us to pack four INT8 multiplications into one DSP blocks on Intel FPGAs [20] to reduce the hardware resources.…”

Resource Optimal Truncated Multipliers for FPGAs

“…Much previous work covers the efficient realization of exact multipliers on FPGAs [7]- [21]. They can be divided into logic-based multipliers [9], [11]- [13], [17], [18], DSP-based multipliers [14], [19], logic/DSP hybrid methods [7], [8], [15], [16], [21] and the efficient summation of partial products in compressor trees [10], [22], [23].…”

“…An efficient mapping for Xilinx FPGAs of a Booth multiplier was proposed in [11]- [13]. In [18], [19], an efficient LUT mapping for small multipliers uses the fractal synthesis approach. To reduce the under-utilization of DSPs, schemes to fit two smaller multiplications in one DSP were studied in [14], [19], [20].…”

“…In [18], [19], an efficient LUT mapping for small multipliers uses the fractal synthesis approach. To reduce the under-utilization of DSPs, schemes to fit two smaller multiplications in one DSP were studied in [14], [19], [20]. The Karatsuba algorithm was used in [7], [16], [21] to trade DSPs for additional logic-based adders or subtractors and a longer critical path.…”