Extending the Roofline Model for Asynchronous Many-Task Runtimes

Suetterlein, Joshua; Landwehr, Joshua; Márquez, Andrés; Manzano, Joseph; Gao, Guang R.

doi:10.1109/cluster.2016.47

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…Denoyelle et al [40] target nodes with heterogeneous memory hierarchies. The authors of [41] modify the Roofline for asynchronous runtimes. Cardwell and Song [42] extend the model for distributed memory systems.…”

Section: Roofline Variationsmentioning

confidence: 99%

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

Gravelle

2022

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In this dissertation, we demonstrate that it is possible to develop methods of empirical hardware-counter-based performance analysis for scientific applications running on diverse CPUs. Although counters have been used in performance analysis for over 30 years, the methods remain limited to particular vendors or generations of CPUs. Our hypothesis is that counter-based measurements could be developed to provide consistent performance information on diverse CPUs. We prove the hypothesis correct by demonstrating one such set of metrics.We begin with an introduction and background discussing empirical performance analysis on CPUs. The background includes the Roofline Performance Model which is widely used to visualize the performance of scientific applications relative to the potential system performance. This model uses metrics that are portable to different CPU architectures, making it a useful starting point for efforts to develop portable hardware counter metrics. We contribute to existing roofline literature by presenting a method using counters to measure the required application data on two CPUs and by presenting benchmarks to produce the Roofline Model of the CPU. These contributions are complementary since the iv benchmarks can be used to validate the hardware counters used to measure the application data.We present a set of performance metrics derived from Hardware Performance Monitors that we have been able to replicate on CPUs from two vendors. We developed these metrics to focus on information that can inform developers about the performance of algorithms and data structures in applications. This method contrasts with other methods which are aimed at microarchitectural features and allows users to understand application performance from the same perspective on multiple CPUs.We use a series of case studies to explore the usefulness of our metrics and to validate that the measured values provide the expected information. The first set of studies examines benchmarks and mini-applications with a variety of performance. Finally, we study the performance of several versions of a scientific application using the Roofline Model and the new metrics. These case studies show that our performance metrics can provide performance information on two CPUs, proving our hypothesis by example.

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Section: Roofline Variationsmentioning

confidence: 99%

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

Gravelle

2022

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“…Lorenzo et al introduce a version of the Rooine model by adding a memory latency dimension [17]. Suetterlein et al extend the model to consider latency hiding and amortized analysis and apply it to asynchronous many-task runtimes [24]. Their model does consider network throughput on distributed memory systems, however, they focus on event-driven tasks rather than the most widely used MPI programming model.…”

Section: A 3d Visualization Of the Extended Rooine Modelmentioning

confidence: 99%

An Extended Roofline Model with Communication-Awareness for Distributed-Memory HPC Systems

Cardwell

Song

2019

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region

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Performance modeling of parallel applications on distributed memory systems is a challenging task due to the eects of CPU speed, memory access time, and communication cost. In this paper, we propose a simple and intuitive graphical model, which extends the widely used Rooine performance model to include the communication cost in addition to the memory access time and the peak CPU performance. This new performance model inherits the simplicity of the original Rooine model and enables performance evaluation on a third dimension of communication performance. Such a model will greatly facilitate and expedite the analysis, development and optimization of parallel programs on high-end computer systems. We empirically validate the extended new Rooine model using oating-point-computation-bound, memory-bound, and communication-bound applications. Three distinct high-end computing platforms have been tested: 1) high performance computing (HPC) systems, 2) high throughput computing systems, and 3) cloud computing systems. Our experimental results with four dierent parallel applications show that the new model can approximately evaluate the performance of dierent programs on various distributed-memory systems. Furthermore, the extended new model is able to provide insight into how the problem size can aect the upper bound performance of parallel applications, which is a special property revealed by the new dimension of communication cost analysis.

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