Extending KrF to 100-nm imaging with high-NA- and chromeless phase lithography technology

Socha, Robert; Broeke, Douglas J. Van Den; Yu, Linda; Conley, Will; Wu, Wei; Chen, J. Fung; Petersen, John S.; Gerold, David J.; Praagh, Judith van; Droste, Richard; Flagello, Donis G.; Hsu, Stephen

doi:10.1117/12.474594

Cited by 4 publications

(4 citation statements)

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“…The effect is that CD errors on the reticle (small delta CD's) appear to be magnified because they are no longer reduced by the magnification factor of the wafer scanner. 13 MEEF = MEAF = δ = δ = δ = δ (CD wafer ) / δ δ δ δ (CD reticle / M ) [4] Some have noted that the reticle errors are neither enhanced nor attenuated, depending upon the process in which the reticle is employed. MEEF = δ = δ = δ = δ (CD wafer ) / δ δ δ δ (CD reticle / M ) [3] However, it is not always the case that the value of this function is greater than or equal to one.…”

Section: Derivative Of the Pattern Transfer Functionmentioning

confidence: 99%

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Tuning MEEF for CD control at 65nm node based on Chromeless Phase Lithography (CPL)

Broeke¹,

Laidig²,

Wampler³

et al. 2002

SPIE Proceedings

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The application of Chromeless Phase Lithography™, or 100% transmission attenuated PSM, has been used to demonstrate the potential for achieving quarter-wavelength optical lithography (0.2k 1 ). 1 As the demand to image sub-100nm features reaches to the semiconductor fabrication lines, the need for a robust lithography process capable of meeting high volume requirements is becoming more and more critical. The requirements for high-volume, low-k 1 semiconductor manufacturing go beyond wafer imaging technology capable of the process latitude needed for lithography, but also includes data prep software that is capable of applying the details of the imaging technology to the design data, correcting for optical proximity effects, and outputting the necessary mask pattern data. It is also necessary to have a reticle manufacturing infrastructure capable of supporting large volume production with reliability and reasonable turn around time.CPL™ technology has, by its nature, many elements that make it a strong candidate to meet mass production requirements for 65nm semiconductor technology products. Most important, CPL achieves the resolution enhancement by using a single reticle and does not require a second exposure with a trim mask. The CPL reticle is a variation of the attenuated phase shifting mask, and data preparation for the reticle manufacturing is very similar to what is needed for high-transmission attenuated PSM. It will be shown that as a result of the 100% transmission, the MEEF for CPL masks is very small and in some cases approaches zero. This allows for much larger CD tolerances for the reticle but results in significant limitations on correcting optical proximity effects by using CD bias alone. Methods for correcting through-pitch CD variations with the use of novel CPL pattern designs, bias, and scattering bars will be presented and correlated to wafer imaging results. These results will demonstrate the ability to control through-pitch CD's while maintaining the beneficial MEEF characteristics of CPL. Experimental results using a CPL reticle designed and manufactured for 65nm lithography exposed on an advanced 193nm ASML /1100 wafer scanner will be presented and discussed. Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/29/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx Proc. of SPIE Vol. 4889 581 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/29/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx Proc. of SPIE Vol. 4889 585 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/29/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

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Section: Derivative Of the Pattern Transfer Functionmentioning

confidence: 99%

“…[2][3][4][5] However, the use of reticle patterns that transmit 100% of the incident energy at a phase of 180 degrees relative to the surrounding field results in some very unique imaging behaviors. The application of this technology to image many different pattern types, including both clear and dark fields, has been demonstrated.…”

Section: Introductionmentioning

confidence: 99%

Tuning MEEF for CD control at 65nm node based on Chromeless Phase Lithography (CPL)

Broeke¹,

Laidig²,

Wampler³

et al. 2002

SPIE Proceedings

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“…PSM have on the line pattern. Therefore, the required resist CD has to be obtained by only phase shift effect and it is difficult to control the resist CD through pitch 1,2) . Especially, when the reticle line CD becomes larger and the phase edge interaction becomes smaller, MEEF decreases and has a negative value 3,4) .…”

Section: Introductionmentioning

confidence: 99%

Performance study of chromeless phase lithography mask for the 65nm node and beyond

et al. 2006

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Chromeless Phase Lithography (CPL) is one of resolution enhancement technologies (RET) for 65nm node and beyond. CPL has various advantages such as no necessity of double exposure, and small pattern displacement and CD error caused by the intensity imbalance. The high resolution lithography can be expected with the combination of high NA and off-axis illumination (OAI) in 193nm lithography. It is known that CPL can flexibly change structure through gate pitch. There are various kinds of structure, such as pure CPL, Zebra, Rim, and Stripe. And there are also various kinds of scattering bar depending on the gate pitch.In this paper, we estimated normalized image log-slope (NILS), mask error enhancement factor (MEEF), depth of focus (DOF) and phase shift depth for each CPL structure by rigorous 3D mask electro-magnetic field (EMF) simulation on mask topographies. And it was found that Zebra and Stripe can improve NILS, and Stripe is most effective to improve MEEF for narrow pitch. There is no large difference in DOF between all structures, and DOF for all structures with wide pitch can be expanded by the addition of chrome scattering bar. We evaluated the impact of phase shift depth and found that the optimal phase shift depth of pure CPL is larger than 180degrees.The improvement of mask-making accuracy becomes more important to achieve better mask pattern resolution. Therefore, we focused on the defects of the sub-resolution chrome feature and chrome scattering bar. It was found that the defects of sub-resolution chrome feature have big influences on the lithography performance. And the defects of scattering bars become more sensitive with closer to the main feature.

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“…Table 1 summarizes the zero and first diffraction order contributions for binary, alternating phase shift mask (altPSM), and Chromeless phase mask (CPL). CPL has the highest first order diffraction amplitude, hence the greatest imaging performance potential [1][2] [3]. It has been demonstrated that CPL could print complex 2D patterns [4].…”

Section: Introductionmentioning

confidence: 99%

Reticle defect printability for sub-0.3k 1 chromeless phase lithography (CPL) technology

Hsu¹,

Broeke²,

Shi³

et al. 2002

SPIE Proceedings

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Chromeless Phase Lithography (CPL) with a high NA exposure tool is shown to be an attractive technology solution for the 65nm node [1]. Under strong image enhancement conditions, the traditional definition of minimum defect printability specifications is no longer adequate. This paper investigates defect printability issues for CPL technology. Based on optimized scattering bar OPC treatments through pitch, a set of defect printability quantification (DPQ) patterns was designed. In the DPQ design, a number of defect types have been programmed with progressively increasing defect size from 0.05(λ/NA) to 0.3(λ/NA). Each defect type and size on the actual CPL reticle were then fully characterized using an advanced CD SEM metrology system, the KLA8450R™ with both wafer and reticle capabilities. This is a very critical step for quantifying defect printability, since in order to accurately assess the printability, the defect dimension must be well correlated to the original DPQ design on the reticle. The DPQ reticle was then printed using a high numerical aperture (NA) scanner (ASML /850™) so that it is possible to characterize the defect printability for each of the programmed defects and the impact on CD through pitch. Minimum printable defect (MPD), maximum non-printable defect (MNPD), and critical dimension (CD) variation percentage were used as metrics to characterize the critical defect size and the sensitivity of each defect type. The purpose of this study is to understand the tolerance of the CLM technology to printable defects and establish a realistic and sensible defect specification.

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Extending KrF to 100-nm imaging with high-NA- and chromeless phase lithography technology

Cited by 4 publications

References 0 publications

Tuning MEEF for CD control at 65nm node based on Chromeless Phase Lithography (CPL)

Tuning MEEF for CD control at 65nm node based on Chromeless Phase Lithography (CPL)

Performance study of chromeless phase lithography mask for the 65nm node and beyond

Reticle defect printability for sub-0.3k 1 chromeless phase lithography (CPL) technology

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