In this paper, a method for improving the process window is described by simultaneous source mask optimization (SMO). The method optimizes the source and mask of a critical pattern by optimizing the mask in the frequency domain. The minimum image log slope (ILS) is maximized at fragmentation points in the critical pattern while simultaneously maintaining the printing fidelity. The mask optimized in the frequency domain is then converted into a chromeless phase lithography (CPL) mask. The process window with the optimized source and optimized CPL mask doubles the aerial image contrast in comparison to an attenuating PSM with source optimization only. After optimizing the mask and source for a critical pattern, the remaining parts of the full-chip design are optimized with interference mapping. Another technique for optimizing the source for a full chip is presented in which the source is optimized by using the pitch frequency of the design. From the pitch frequency, the source is optimized by solving an integral equation for the first eigenfunction in which the first eigenfunction is calculated from the sum of coherent system (SOCS) representation of the transfer cross coefficient (TCC).
The optimization of the source topology and mask design [1,2] is vital to future advanced ArF technology node development. In this study, we report the comparison of an iterative optimization method versus a newly developed simultaneous source-mask optimization approach. In the iterative method, the source is first optimized based on normalized image log slopes (NILS), taking into account the ASML scanner's diffractive optical element (DOE) manufacturability constraints. Assist features (AFs) are placed under the optimized source, and then optical proximity correction (OPC) is performed using the already placed AFs, in the last step the source is re-optimized using the OPC-ed layout with the AFs. The source is then optimized using the layout from the previous stage based on a set of user specified cost function. The new approach first co-optimizes a pixelated freeform source and a continuous transmission gray tone mask based on edge placement error (EPE) based cost function. ASML scanner specific constraints are applied to the optimized source, to match ASML's current and future illuminator capabilities. Next, AF "seeds" are identified from the optimized gray tone mask, which are subsequently co-optimized with the main features to meet the process window and mask error factor requirement. The results show that the new method offers significant process window improvement.
Double patterning technology (DPT) is a promising technique that bridges the anticipated technology gap from the use of 193nm immersion to EUV for the half-pitch device node beyond 45nm. The intended mask pattern is formed by two independent patterning steps. Using DPT, there is no optical imaging correlation between the two separate patterning steps except for the impact from mask overlay. In each of the single exposure step, we can relax the dense design pattern pitches by decomposing them into two half-dense ones. This allows a higher k 1 imaging factor for each patterning step. With combined patterns, we can achieve overall k 1 factor that exceeds the conventional Rayleigh resolution limit. This paper addresses DPT application challenges with respect to both mask error factor (MEF) and 2D patterning. In our simulations using DPT with relaxed feature pitch for each exposure step, the MEF for the line/space is fairly manageable for 32nm half-pitch and below. The real challenge for the 32nm half-pitch and below with DPT is how to deal with the printing of small 2D features resulting from the many cutting sites due to feature decomposition. Each split of a dense pattern generates two difficult-to-print line-end type features with dimension less than one-fifth or onesixth of ArF wavelength. Worse, the proximity environment of the 2D cut features can then become quite complex. How to stitch them correctly back to the original target requires careful attention. Applying target bias can improve the printing performance in general. But using a model-based stitching error correction method seems to be a preferred solution.
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