Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets

Gondhalekar, Atharva; Feng, Wu-chun

doi:10.1109/fpl50879.2020.00032

Cited by 5 publications

(3 citation statements)

References 22 publications

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“…Running various signal processing functions (e.g., different waveform shaping techniques from other running slices) on shared heterogeneous SDR architectures brings the challenge of irregular runtime adaptation (IRA) to the iRAN-S scene. IRA was examined for graph algorithms design in high-performance computing (HPC) [13]. In [13], authors discussed the runtime adaptation between various parallelizing techniques for irregular applications that run across shared heterogeneous architectures.…”

Section: Directions For Future Researchmentioning

confidence: 99%

“…IRA was examined for graph algorithms design in high-performance computing (HPC) [13]. In [13], authors discussed the runtime adaptation between various parallelizing techniques for irregular applications that run across shared heterogeneous architectures. Irregularity at runtime could arise due to several reasons, such as irregular memory access patterns (IMA) and irregular workload distribution (IWD).…”

Section: Directions For Future Researchmentioning

confidence: 99%

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Towards Intelligent RAN Slicing for B5G: Opportunities and Challenges

Mazied,

Liu,

Midkiff

2021

Preprint

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To meet the diverse demands for wireless communication, fifth-generation (5G) networks and beyond (B5G) embrace the concept of network slicing by forging virtual instances (slices) of its physical infrastructure. While network slicing constitutes dynamic allocation of core network and radio access network (RAN) resources, this article emphasizes RAN slicing (RAN-S) design. Forming on-demand RAN-S that can be flexibly (re)-configured while ensuring slice isolation is challenging. A variety of machine learning (ML) techniques have been recently introduced for traffic forecasting and classification, resource usage prediction, admission control, scheduling, and dynamic resource allocation in RAN-S. Albeit these approaches grant opportunities towards intelligent RAN-S design, they raise critical challenges that need to be examined. This article underlines the opportunities and the challenges of incorporating ML into RAN-S by reviewing the cutting-edge ML-based techniques for RAN-S. It also draws few directions for future research towards intelligent RAN-S (iRAN-S).

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Section: Directions For Future Researchmentioning

confidence: 99%

Section: Directions For Future Researchmentioning

confidence: 99%

Towards Intelligent RAN Slicing for B5G: Opportunities and Challenges

Mazied,

Liu,

Midkiff

2021

Preprint

View full text Add to dashboard Cite

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“…Here, OpenCL uses synchronous queue execution, in which the program waits until the executed command ends. Synchronous queue execution has the limitation of delaying the processing speed of a host, because the right to control the command that is executed in a computing device does not return to the host until the command ends, and this induces kernel launch overhead [50]. Therefore, our framework processes each OpenCL command in an asynchronous manner, thus maximizing GPU utilization.…”

Section: Asynchronous Queue Executionmentioning

confidence: 99%

CitiusSynapse: A Deep Learning Framework for Embedded Systems

2021

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As embedded systems, such as smartphones with limited resources, have become increasingly popular, active research has recently been conducted on performing on-device deep learning in such systems. Therefore, in this study, we propose a deep learning framework that is specialized for embedded systems with limited resources, the operation processing structure of which differs from that of standard PCs. The proposed framework supports an OpenCL-based accelerator engine for accelerator deep learning operations in various embedded systems. Moreover, the parallel processing performance of OpenCL is maximized through an OpenCL kernel that is optimized for embedded GPUs, and the structural characteristics of embedded systems, such as unified memory. Furthermore, an on-device optimizer for optimizing the performance in on-device environments, and model converters for compatibility with conventional frameworks, are provided. The results of a performance evaluation show that the proposed on-device framework outperformed conventional methods.

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