Exploring design diversity redundancy to improve resilience in mixed-signal systems

Chenet, Cristiano P.; Tambara, Lucas Antunes; Borges, Gabriel de Morais; Kastensmidt, Fernanda Lima; Lubaszewski, Marcelo; Balen, Tiago R.

doi:10.1016/j.microrel.2015.08.011

Cited by 10 publications

(8 citation statements)

References 12 publications

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“…The architecture tested in all the experimentes herin presented is a fault tolerant data acquisition system (DAS), proposed by our research group in [7]. The system was fully implemented in a commercial Programmable SoC (PSoC 5 from Cypress Semiconductor -now Infineon) manufactured in a 130 nm CMOS technology.…”

Section: Device and Design Under Testmentioning

confidence: 99%

“…Therefore, as important as the correct functioning of computing units and digital system parts, is the reliability of analog-todigital (AD) and digital-to-analog (DA) system interfaces. Examples of works in which reliability to radiation effects and mitigation techniques were evaluated in such blocks can be found in [5,6,7,8,9,10,11].…”

Section: Introductionmentioning

confidence: 99%

“…In a previous work of our research group a faulttolerant data acquisition system (DAS) was proposed to cope with radiation effects and other environmental degradation sources [7,12,13,14]. The system was designed and programmed in a Commercial Programmable System-on-Chip (PSoC) from Cypress Semiconductor (now Infineon Technologies) [15] fabricated in a 130 nm CMOS process.…”

Section: Introductionmentioning

confidence: 99%

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Testing a Fault Tolerant Mixed-Signal Design Under TID and Heavy Ions

González

Machado

Vaz³

et al. 2021

JICS

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This work presents results of three distinct radiation tests performed upon a fault-tolerant data acquisition system comprising a design diversity redundancy technique. The first and second experiments are Total Ionizing Dose (TID) essays, comprising gamma and X-ray irradiations. The last experiment considers single event effects, in which two heavy ion irradiation campaigns are carried out. The case study system comprises three analog-to-digital converters and two software-based voters, besides additional software and hardware resources used for controlling, monitoring and memory management. The applied Diversity Triple Modular Redundancy (DTMR) technique, comprises different levels of diversity (temporal and architectural). The circuit was designed in a programmable System-on-Chip (PSoC), fabricated in a 130nm CMOS technology process. Results show that the technique may increase the lifetime of the system under TID if comparing with a non-redundant implementation. Considering the heavy ions experiments the system was proved effective to tolerate 100% of the observed errors originated in the converters, while errors in the processing unit present a higher criticality. Critical errors occurring in one of the voters were also observed. A second heavy-ion campaign was then carried out to investigate the voters reliability, comparing the dynamic cross-section of three different software-based voter schemes implemented in the considered PSoC.

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Section: Device and Design Under Testmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Testing a Fault Tolerant Mixed-Signal Design Under TID and Heavy Ions

González

Machado

Vaz³

et al. 2021

JICS

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“…In [4], the application of DTMR to mixed-signal (MS) circuits was addressed, identifying the possible modes of diversity implementation (time, domain, level and architecture) and the drawbacks of applying this technique do MS systems. One of the case studies of the mentioned work is a data acquisition system implementing the DTMR technique with hardware and time diversity.…”

Section: B Fault Tolerance With Design Diversitymentioning

confidence: 99%

“…In previous works of our research group [4], [12], we proposed the application of a mitigation strategy based on modular redundancy with design diversity to a data acquisition system, prototyped in a PSoC (Programmable System-on-Chip) device. In the mentioned works, a compiled-time fault injection was carried out, by manually inserting bit-flips in few registers of the architecture, since the purpose was only to validate the spatial-temporal voting scheme proposed in those works.…”

Section: Introductionmentioning

confidence: 99%

Fault Injection on a Mixed-Signal Programmable SoC with Design Diversity Mitigation

Aguilera¹,

Chenet²,

Balen³

2020

JICS

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This paper presents an approach for runtime software-based fault injection, applied to a commercial mixed-signal programmable system-on-chip (PSoC). The fault-injection scheme is based on a pseudo-random sequence generator and software interruption. A fault tolerant data acquisition system, based on a design diversity redundant scheme, is considered as case study. The fault injection is performed by intensively inserting bit flips in the peripherals control registers of the mixed-signal PSoC blocks, as well as in the SRAM memory of the device. Results allow to evaluate the applied fault tolerance technique, indicating that the system is able to tolerate most of the generated errors. Additionally, a high fault masking effect is observed, and different criticality levels are observed for faults injected into the SRAM memory and in the peripherals control registers.

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