Exploiting temporal locality in drowsy cache policies

Abstract

Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage of the overall microprocessor die area. Therefore, recent research has concentrated on the reduction of leakage current dissipated by caches. The variety of techniques to control current leakage can be classified as non-state preserving or state preserving. Non-state preserving techniques power off selected cache lines while state preserving place selected lines into a low-power state. Drowsy caches are a recently proposed state-preserving technique. In order to introduce low performance overhead, drowsy caches must be very selective on which cache lines are moved to a drowsy state.Past research on cache organization has focused on how best to exploit the temporal locality present in the data stream. In this paper we propose a novel drowsy cache policy called Reuse Most Recently used On (RMRO), which makes use of reuse information to trade off performance versus energy consumption. Our proposal improves the hit ratio for drowsy lines by about 67%, while reducing the power consumption by about 11.7% (assuming 70nm technology) with respect to previously proposed drowsy cache policies.

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

“…Cache Decay relies on fine-grained logic counters, which are expensive, especially for large lower-level caches. Drowsy Caches [8,23] periodically move inactive lines to a low power mode in which they cannot be read or written. However, this scheme is less applicable in deep-nm technology nodes, where the difference between V dd and V t will be smaller.…”

Combining RAM Technologies for Hard-error Recovery in L1 Data Caches Working at Very-low Power Modes

“…In L1 caches, more than 90% of cache accesses hit the Most Recently Used (MRU) way [14]. Thus, to achieve good performance, in the HER cache the MRU block of each cache set is always stored in an SRAM bank.…”

Cache architectures based on heterogeneous technologies to deal with manufacturing errors

“…The idea is to keep the data most recently used (MRU) by the processor always in the SRAM cell. Previous works [37] have shown that the MRU line in each cache set use to be accessed with a much higher probability than the remaining ones (for instance, 92.15% of the accesses in a 16KB-4way L1). Therefore, keeping the MRU data in the SRAM cell might provide energy benefits because SRAM reads are non-destructive.…”

“…The techniques falling in the second group put the selected lines into a state-preserving low-power mode [14,37], reaching the same hit rate as a conventional cache. However, they reduce less leakage since the lines are not completely turned off.…”