Exploiting symmetry in temporal logic model checking

Clarke, Edmund M.; Enders, Reinhard; Filkorn, Thomas; Jha, Somesh

doi:10.1007/bf00625969

Cited by 261 publications

(150 citation statements)

References 7 publications

Supporting

Mentioning

146

Contrasting

Order By: Relevance

“…In hardware verification, techniques with the same goal exist and usually work by altering these BDDs during the search. Some of these techniques try to exploit special structures in the circuits, such as symmetries [27] or asynchrony [28]. Because our models lack these special structures, these techniques are not applicable.…”

Section: Discussion and Related Workmentioning

confidence: 99%

Optimizing symbolic model checking for statecharts

Chan

Anderson

Beame

et al. 2001

IIEEE Trans. Software Eng.

View full text Add to dashboard Cite

AbstractÐSymbolic model checking based on binary decision diagrams is a powerful formal verification technique for reactive systems. In this paper, we present various optimizations for improving the time and space efficiency of symbolic model checking for systems specified as statecharts. We used these techniques in our analyses of the models of a collision avoidance system and a faulttolerant electrical power distribution (EPD) system, both used on commercial aircraft. The techniques together reduce the time and space requirements by orders of magnitude, making feasible some analysis that was previously intractable. We also elaborate on the results of verifying the EPD model. The analysis disclosed subtle modeling and logical flaws not found by simulation.

show abstract

Section: Discussion and Related Workmentioning

confidence: 99%

Optimizing symbolic model checking for statecharts

Chan

Anderson

Beame

et al. 2001

IIEEE Trans. Software Eng.

View full text Add to dashboard Cite

show abstract

“…We want to be able to restrict the test process to subautom ata of specification and imple m entation that characterize these systems up to symmetry. In papers on exploiting symmetry in model checking [2,8,10,11,12,18], such subautom ata are constructed for explicitly given FSMs by identifying and collapsing symmetrical states. We are concerned with black box testing, and, by definition, it is impossible to refer directly to the states of a black box.…”

Section: Symmetrymentioning

confidence: 99%

Exploiting Symmetry in Protocol Testing

Romijn

Springintveld

1998

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

Test generation and execution are often hampered by the large state spaces of the systems involved. In automata (or transition system) based test algorithms, taking advantage of symmetry in the behavior of specification and implementation may substantially reduce the amount of tests. We present a framework for describing and exploiting symmetries in black box test derivation methods based on finite state machines (FSMs). An algorithm is presented that, for a given symmetry relation on the traces of an FSM, computes a subautomaton that characterizes the FSM up to symmetry. This machinery is applied to Chow's classical W-method for test derivation. Finally, we focus on symmetries defined in terms of repeating patterns.

show abstract

“…The state space is reduced by considering global states equivalent that are identical up to applications of structure automorphisms, for example permutations that interchange the identities of participating components. This equivalence, the orbit relation, gives rise to a bisimilar quotient structure over the equivalence classes (orbits) [ES96,CEFJ96].…”

Section: Introductionmentioning

confidence: 99%

“…Disappointingly, it was discovered that symbolic representation using BDDs, by then becoming a standard in large-scale system verification, seemed not to combine favorably with symmetry reduction [CEFJ96]. The reason is that the BDD for the orbit relation is provably intractably large.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Symmetry Reduction

Wahl

2005

Tools and Algorithms for the Construction and Analysis of Systems

View full text Add to dashboard Cite

Abstract. Symmetry reduction is a technique to combat the state explosion problem in temporal logic model checking. Its use with symbolic representation has suffered from the prohibitively large BDD for the orbit relation. One suggested solution is to pre-compute a mapping from states to possibly multiple representatives of symmetry equivalence classes. In this paper, we propose a more efficient method that determines representatives dynamically during fixpoint iterations. Our scheme preserves the uniqueness of representatives. Another alternative to using the orbit relation is counter abstraction. It proved efficient for the special case of full symmetry, provided a conducive program structure. In contrast, our solution applies also to systems with less than full symmetry, and to systems where a translation into counters is not feasible. We support these claims with experimental results.

show abstract

Exploiting symmetry in temporal logic model checking

Cited by 261 publications

References 7 publications

Optimizing symbolic model checking for statecharts

Optimizing symbolic model checking for statecharts

Exploiting Symmetry in Protocol Testing

Dynamic Symmetry Reduction

Contact Info

Product

Resources

About