Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design

Ashammagari, Adarsh Reddy; Mahmoodi, Hamid; Homayoun, Houman

doi:10.7873/date2014.348

Cited by 1 publication

(1 citation statement)

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“…Due to its non-volatile nature and CMOS compatibility, STT-based memory (STT-RAM) has shown great promise in addressing the leakage barrier for SRAM. While the high write power still remains to be a major obstacle for STTRAM [3], the application of STT-based memory in reconfigurable logic, as in Field Programmable Gate Arrays (FPGA) or reconfigurable functional units, seems more promising due to the low frequency of reconfiguration where the write power occurs [4,25,26]. Reconfigurable logic relies on implementing logic in small Look-Up- Tables (LUT).…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Kuttappa

Homayoun

Salmani

et al. 2016

Microelectronics Reliability

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Spin Transfer Torque (STT) switching realized using a Magnetic Tunnel Junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile Look Up Tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16nm bulk CMOS, for the same total device area, the voltage sensing scheme offers 17% to 28% lower failure rates under combined intra-die transistor and MTJ variations, comparable delay, and 56% lower active power compared to the current sensing scheme. Moreover, we compare the reliability of the two sensing schemes under Negative Bias Temperature Instability (NBTI) of PMOS transistors. Our results indicate that the failures rates increase over time by transistor aging for both designs, and the voltage sensing scheme maintains its improved failure rate over to the current sensing scheme.

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