Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation

Yang, Jianlei; Wang, Xueyan; Zhou, Qiang; Wang, Zhaohao; Li, Hai; Chen, Yiran; Zhao, Weisheng

doi:10.1109/tcad.2018.2802870

Cited by 28 publications

(23 citation statements)

References 39 publications

(67 reference statements)

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“…The read circuit consists of a two-branch sensing circuit with equalizing transistors [38] and a voltage sense amplifier with dynamic latched comparator [39] for digital output. Both branches of read circuit are composed by a load pMOS, a read enable nMOS and a clamped nMOS [40] [41]. The read operation is enabled by setting Read En.…”

Section: Spintronic Device Based Energy Efficient Sbgmentioning

confidence: 99%

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Jia

Yang

Dai

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computingintensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this work, a spintronics based stochastic computing approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build stochastic bitstream generator (SBG) for stochastic computing with hybrid CMOS/MTJ circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and stochastic computing logic. A deviceto-architecture level framework is proposed to evaluate the performance of spintronics based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about 12× than MTJ-based approach with 45% design area overhead and about 26× than FPGA-based approach.

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Section: Spintronic Device Based Energy Efficient Sbgmentioning

confidence: 99%

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Jia

Yang

Dai

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Considering that the authors leverage the relatively old TSMC 0.35µm library, the related overheads per SOT-LUT device could become prohibitive for large-scale camouflaging, especially in the context of modern CMOS nodes (as we consider for ours). Hence, we believe that our scheme can be superior to that of [44].…”

Section: Cost and Comparison Of The Gshe Security Primitivementioning

confidence: 88%

“…For CMOS integration, various techniques have been proposed, e.g., look-alike gates [37], threshold-voltage-dependent (TVD) camouflaging [38], [39], and camouflaging of the interconnects [40]. Emerging devices have been recently considered for camouflaging as well, e.g., in [41]- [44]; see also Sec. II-E and Sec.…”

Section: Hardware Securitymentioning

confidence: 99%

“…In contrast, our switch can implement all 16 functions within one device, with peripheral circuitry only required for transduction and obfuscation purposes. Second, the primitive in [44] is not inherently polymorphic; hence, it can only support static camouflaging. Third, recall that the authors obfuscated only 16/32/64 gates.…”

Section: Cost and Comparison Of The Gshe Security Primitivementioning

confidence: 99%

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Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Patnaik

Rangarajan

Knechtel³

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Protecting intellectual property (IP) has become a serious challenge for chip designers. Most countermeasures are tailored for CMOS integration and tend to incur excessive overheads, resulting from additional circuitry or device-level modifications. On the other hand, power density is a critical concern for sub-50 nm nodes, necessitating alternate design concepts. Although initially tailored for error-tolerant applications, imprecise computing has gained traction as a general-purpose design technique. Emerging devices are currently being explored to implement ultra-low-power circuits for inexact computing applications. In this paper, we quantify the security threats of imprecise computing using emerging devices. More specifically, we leverage the innate polymorphism and tunable stochastic behavior of spin-orbit torque (SOT) devices, particularly, the giant spin-Hall effect (GSHE) switch. We enable IP protection (by means of logic locking and camouflaging) simultaneously for deterministic and probabilistic computing, directly at the GSHE device level. We conduct a comprehensive security analysis using state-of-the-art Boolean satisfiability (SAT) attacks; this study demonstrates the superior resilience of our GSHE primitive when tailored for deterministic computing. We also demonstrate how probabilistic computing can thwart most, if not all, existing SAT attacks. Based on this finding, we propose an attack scheme called probabilistic SAT (PSAT) which can bypass the defense offered by logic locking and camouflaging for imprecise computing schemes. Further, we illustrate how careful application of our GSHE primitive can remain secure even on the application of the PSAT attack. Finally, we also discuss side-channel attacks and invasive monitoring, which are arguably even more concerning threats than SAT attacks.

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“…Technology heterogeneity recognizes the cooperating advantages of CMOS devices for their rapid switching capabilities, while simultaneously embracing emerging devices for their non-volatility, near-zero standby power, high integration density, and radiation-hardness. For instance, spintronicbased LUTs are proposed in [8], [9], [10] as the primary building blocks in reconfigurable fabrics realizing significant area and energy consumption savings. In this paper, we extend the transition toward heterogeneity along various logic paradigms by proposing a heterogeneous technology fabric realizing both probabilistic and deterministic computational models.…”

Section: Introductionmentioning

confidence: 99%

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks

Zand

DeMara

2018

2018 IEEE International Conference on Rebooting Computing (ICRC)

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In this paper, a spintronic neuromorphic reconfigurable Array (SNRA) is developed to fuse together power-efficient probabilistic and in-field programmable deterministic computing during both training and evaluation phases of restricted Boltzmann machines (RBMs). First, probabilistic spin logic devices are used to develop an RBM realization which is adapted to construct deep belief networks (DBNs) having one to three hidden layers of size 10 to 800 neurons each. Second, we design a hardware implementation for the contrastive divergence (CD) algorithm using a four-state finite state machine capable of unsupervised training in N+3 clocks where N denotes the number of neurons in each RBM. The functionality of our proposed CD hardware implementation is validated using ModelSim simulations. We synthesize the developed Verilog HDL implementation of our proposed test/train control circuitry for various DBN topologies where the maximal RBM dimensions yield resource utilization ranging from 51 to 2,421 lookup tables (LUTs). Next, we leverage spin Hall effect (SHE)-magnetic tunnel junction (MTJ) based non-volatile LUTs circuits as an alternative for static random access memory (SRAM)-based LUTs storing the deterministic logic configuration to form a reconfigurable fabric. Finally, we compare the performance of our proposed SNRA with SRAMbased configurable fabrics focusing on the area and power consumption induced by the LUTs used to implement both CD and evaluation modes. The results obtained indicate more than 80% reduction in combined dynamic and static power dissipation, while achieving at least 50% reduction in device count.

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Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation

Cited by 28 publications

References 39 publications

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

SNRA: A Spintronic Neuromorphic Reconfigurable Array for In-Circuit Training and Evaluation of Deep Belief Networks

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