Exploiting spare resources of in-order SMT processors executing hard real-time threads

Mische, Jörg; Uhrig, Sascha; Kluge, Florian; Ungerer, Theo

doi:10.1109/iccd.2008.4751887

Cited by 15 publications

(14 citation statements)

References 10 publications

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“…We used the Hightec GNU C/C++ compiler for TriCore [15] to compile benchmark programs from the EEMBC AutoBech 1.1 benchmark suite [20] (a2time, canrdr, aifirf, rspeed) and the Mälardalen WCET group [21] (crc, fft1, mm). When executing multiple threads, the HPT reaches exactly 100% of its singlethreaded speed, hence a WCET analysis for a singlethreaded simplification of our architecture is also valid for the HPT in the multithreaded architecture [17]. The speed of the threads with lower priorities fall exponentially to about 50, 35 and 20 percent of single threaded performance (measured in Instructions Per Cycle, IPC).…”

Section: Discussionmentioning

confidence: 99%

“…The speed of the threads with lower priorities fall exponentially to about 50, 35 and 20 percent of single threaded performance (measured in Instructions Per Cycle, IPC). For a more detailed discussion see [17].…”

Section: Discussionmentioning

confidence: 99%

“…With this technique, sophisticated scheduling algorithms for multiple hard real-time threads [17] or overlapping IPC controlled threads [18] can be implemented.…”

Section: Real-time Issuementioning

confidence: 99%

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How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

Mische

Guliashvili

Uhrig

et al. 2010

Architecture of Computing Systems - ARCS 2010

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Abstract. This paper describes how a superscalar in-order processor must be modified to support Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real-time applications. For superscalar in-order architectures the calculation of the Worst Case Execution Time (WCET) is much easier and tighter than for out-of-order architectures. By a careful enhancement that completely isolates the threads, this capability can be perpetuated to an in-order SMT architecture. Our design goal is to minimise the WCET of the highest priority thread, while releasing as many resources as possible for the execution of concurrent non critical threads. The resultant processor executes hard real-time threads at the same speed as its singlethreaded ancestor, but idle issue slots are dynamically used by non critical threads. The modifications to enable SMT include a multithreaded fetch stage, an additional real-time issue stage, a wider register set, a prioritised multithreaded memory interface, split phase loads and interruptible microcodes for multi-cycle operations. The application of these enhancements is demonstrated by CarCore, a multithreaded embedded processor that implements the Infineon Tricore instruction set.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

Mische

Guliashvili

Uhrig

et al. 2010

Architecture of Computing Systems - ARCS 2010

Self Cite

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“…Work along these lines includes classifications of existing microarchitectures in terms of their predictability [17], [20], studies of the predictability of caches [6], and proposals of new microarchitectural techniques, such as novel multithreaded architectures that eliminate interference between threads [21], [22], [23], [24], [25] and DRAM controllers that allow multiple tasks to share DRAM devices in a predictable and composable fashion [26], [27]. In the following, we review work specifically concerning the interplay between multitasking and the memory hierarchy.…”

Section: Related Workmentioning

confidence: 99%

Selfish-LRU: Preemption-aware caching for predictability and performance

Reineke

Altmeyer

Grund

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Abstract-We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement policy that improves performance and predictability in preemptive scheduling scenarios.In multitasking systems with conventional caches, a single memory access by a preempting task can trigger a chain reaction leading to a large number of additional cache misses in the preempted task. Selfish-LRU prevents such chain reactions by first evicting cache blocks that do not belong to the currently active task. Simulations confirm that Selfish-LRU reduces the CRPD (cache-related preemption delay) as well as the overall number of cache misses. At the same time, it simplifies CRPD analysis and results in smaller CRPD bounds.

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“…In particular, Mische et al [12] used a simultaneous mulithreaded architecture and assigned a top priority to a thread dedicated as the real-time thread. The architecture was modified slightly to allow interruption of instruction execution and rollback.…”

Section: Microarchitecturementioning

confidence: 99%

Temporal isolation on multiprocessing architectures

Bui

Lee

Liu

et al. 2011

Proceedings of the 48th Design Automation Conference

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Multiprocessing architectures provide hardware for executing multiple tasks simultaneously via techniques such as simultaneous multithreading and symmetric multiprocessing. The problem addressed by this paper is that even when tasks that are executing concurrently do not communicate, they may interfere by affecting each other's timing. For cyberphysical system applications, such interference can nullify many of the advantages offered by parallel hardware. In this paper, we argue for temporal semantics in layers of abstraction in computing. This will enable us to achieve temporal isolation on multiprocessing architectures. We discuss techniques at the microarchitecture level, in the memory hierarchy, in on-chip communication, and in the instruction-set architecture that can provide temporal semantics and control over timing.

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Exploiting spare resources of in-order SMT processors executing hard real-time threads

Cited by 15 publications

References 10 publications

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT

Selfish-LRU: Preemption-aware caching for predictability and performance

Temporal isolation on multiprocessing architectures

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