Exploiting reference idempotency to reduce speculative storage overflow

Kim, Seon Wook; Ooi, Chong-Liang; Eigenmann, Rudolf; Falsafi, Babak; Vijaykumar, T. N.

doi:10.1145/1152649.1152653

Cited by 15 publications

(9 citation statements)

References 12 publications

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“…Table 1 classifies prior work in terms of its application domain and the level at which idempotence is used and identified [2,9,10,12,16,19,21,23,25,31,36]. One of the earliest uses is by Mahlke et al in using restartable instruction sequences for exception recovery in speculative processors [23].…”

Section: Introductionmentioning

confidence: 99%

Static analysis and compiler design for idempotent processing

Kruijf

Sankaralingam

Jha

2012

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation

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Recovery functionality has many applications in computing systems, from speculation recovery in modern microprocessors to fault recovery in high-reliability systems. Modern systems commonly recover using checkpoints. However, checkpoints introduce overheads, add complexity, and often save more state than necessary.This paper develops a novel compiler technique to recover program state without the overheads of explicit checkpoints. The technique breaks programs into idempotent regions-regions that can be freely re-executed-which allows recovery without checkpointed state. Leveraging the property of idempotence, recovery can be obtained by simple re-execution. We develop static analysis techniques to construct these regions and demonstrate low overheads and large region sizes for an LLVM-based implementation. Across a set of diverse benchmark suites, we construct idempotent regions close in size to those that could be obtained with perfect runtime information. Although the resulting code runs more slowly, typical performance overheads are in the range of just 2-12%.The paradigm of executing entire programs as a series of idempotent regions we call idempotent processing, and it has many applications in computer systems. As a concrete example, we demonstrate it applied to the problem of compiler-automated hardware fault recovery. In comparison to two other state-of-the-art techniques, redundant execution and checkpoint-logging, our idempotent processing technique outperforms both by over 15%.

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Section: Introductionmentioning

confidence: 99%

Static analysis and compiler design for idempotent processing

Kruijf

Sankaralingam

Jha

2012

Proceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation

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“…The concept of idempotence has been leveraged by Kim et al in the context of thread-level speculation to allow idempotent references to see speculative state [30]. Additionally, Shivers et al use idempotence to achieve atomicity guarantees for garbage collectors [36].…”

Section: Related Workmentioning

confidence: 99%

Idempotent processor architecture

Kruijf

Sankaralingam

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Improving architectural energy efficiency is important to address diminishing energy efficiency gains from technology scaling. At the same time, limiting hardware complexity is also important. This paper presents a new processor architecture, the idempotent processor architecture, that advances both of these directions by presenting a new execution paradigm that allows speculative execution without the need for hardware checkpoints to recover from misspeculation, instead using only re-execution to recover. Idempotent processors execute programs as a sequence of compilerconstructed idempotent (re-executable) regions. The nature of these regions allows precise state to be reproduced by re-execution, obviating the need for hardware recovery support. We build upon the insight that programs naturally decompose into a series of idempotent regions and that these regions can be large. The paradigm of executing idempotent regions, which we call idempotent processing, can be used to support various types of speculation, including branch prediction, dependence prediction, or execution in the presence of hardware faults or exceptions.In this paper, we demonstrate how idempotent processing simplifies the design of in-order processors. Conventional in-order processors suffer from significant complexities to achieve high performance while supporting the execution of variable latency instructions and enforcing precise exceptions. Idempotent processing eliminates much of these complexities and the resulting inefficiencies by allowing instructions to retire out of order with support for re-execution when necessary to recover precise state. Across a diverse set of benchmark suites, our quantitative results show that we obtain a geometric mean performance increase of 4.4% (up to 25% and beyond) while maintaining an overall reduction in power and hardware complexity.

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“…In [7], Garzarán et al analyzed the trade-offs between the various approaches for buffering memory state in the context of TLS. Recently, Kim et al proposed a mechanism based on exploiting reference idempotency to reduce buffer overflow [8]. However, they used the train data set which are significantly smaller than the reference data sets.…”

Section: Recursionmentioning

confidence: 99%