Exploiting Redundancy to Speedup Reconfiguration of an FPGA

Kennedy, Irwin O.

doi:10.1007/978-3-540-45234-8_26

Cited by 19 publications

(12 citation statements)

References 1 publication

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“…Our technique focuses on the unit of configuration. Recently, Kennedy has performed experiments that are somewhat similar to ours [8]. While we confirm his findings that as much as 80% of the configurations can be redundant while changing a typical circuit into another, our techniques are essentially different.…”

Section: Introductionsupporting

confidence: 81%

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On the placement and granularity of FPGA configurations

Malik

Diessel

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

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Section: Introductionsupporting

confidence: 81%

“…This is very much a device specific issue and will not be considered in detail. For a discussion on this, please see [8].…”

Section: Datamentioning

confidence: 99%

On the placement and granularity of FPGA configurations

Malik

Diessel

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

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“…[7,16,6]). We are currently investigating the possibility of caching the update bytes in our method.…”

Section: Discussionmentioning

confidence: 99%

A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs

Torre

Malik

Diessel

2005

Advances in Computer Systems Architecture

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Abstract. This paper presents an investigation and design of an enhanced on-chip configuration memory system that can reduce the time to (re)configure an FPGA. The proposed system accepts configuration data in a compressed form and performs decompression internally. The resulting FPGA can be (re)configured in time proportional to the size of the compressed bit-stream. The compression technique exploits the redundancy present in typical configuration data. An analysis of configurations corresponding to a set of benchmark circuits reveals that data that controls the same types of configurable elements have a common byte that occurs at a significantly higher frequency. This common byte is simply broadcast to all instances of that element. This step is followed by byte updates if required. The new configuration system has modest hardware requirements and was observed to reduce reconfiguration time for the benchmark set by two-thirds on average.

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“…MC-FPGAs have a high degree of redundancy in configuration data between contexts [4], [12]. That is, in MC-FPGAs, less than 3% of configuration data are changed when contexts are switched.…”

Section: Area-efficient Switch Block Architecture and Evaluationmentioning

confidence: 99%

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals

Ishihara

Idobata

Hariyama

et al. 2010

IEICE Trans. Inf. & Syst.

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SUMMARYDynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiplevalued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 µm-CMOS/0.60 µm-ferroelectric-capacitor process. The transistor count of the proposed multicontext switch block is reduced to 63% in comparison with that of the SRAM-based one. key words: dynamically programmable gate array, multi-context switch, logic-in-memory circuit, multiple-valued threshold logic, nonvolatile storage, non-destructive operation

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Exploiting Redundancy to Speedup Reconfiguration of an FPGA

Cited by 19 publications

References 1 publication

On the placement and granularity of FPGA configurations

On the placement and granularity of FPGA configurations

A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals

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