Exploiting Longer SIMD Lanes in Dynamic Binary Translation

Hong, Ding-Yong; Fu, Sheng-Yu; Liu, Yuping; Wu, Jan‐Jan; Hsu, Wei-Chung

doi:10.1109/icpads.2016.0115

Cited by 7 publications

(4 citation statements)

References 8 publications

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“…However, they have very different objectives and approaches in their designs. The most closely related works are Hallou et al (2016), Hallou et al (2015), and Hong et al (2016), which present vectorization schemes from short SIMD to long SIMD for loops. Hallou et al designed their work in a same-ISA DBT for the x86 architecture, while Hong et al proposed a cross-ISA solution.…”

Section: Related Workmentioning

confidence: 99%

Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation

Liu

Hong

et al. 2019

ACM Trans. Archit. Code Optim.

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Single instruction multiple data (SIMD) has been adopted for decades because of its superior performance and power efficiency. The SIMD capability (i.e., width, number of registers, and advanced instructions) has diverged rapidly on different SIMD instruction-set architectures (ISAs). Therefore, migrating existing applications to another host ISA that has fewer but longer SIMD registers and more advanced instructions raises the issues of asymmetric SIMD capability. To date, this issue has been overlooked and the host SIMD capability is underutilized, resulting in suboptimal performance. In this article, we present a novel binary translation technique called spill-aware superword level parallelism (saSLP), which combines short ARMv8 instructions and registers in the guest binaries to exploit the x86 AVX2 host's parallelism, register capacity, and gather instructions. Our experiment results show that saSLP improves the performance by 1.6× (2.3×) across a number of benchmarks and reduces spilling by 97% (99%) for ARMv8 to x86 AVX2 (AVX-512) translation. Furthermore, with AVX2 (AVX-512) gather instructions, saSLP speeds up several data-irregular applications that cannot be vectorized on ARMv8 NEON by up to 3.9× (4.2×).

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Section: Related Workmentioning

confidence: 99%

Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation

Liu

Hong

et al. 2019

ACM Trans. Archit. Code Optim.

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“…Hong et al [11,13] proposed using a machine-independent IR layer to achieve cross-ISA SIMD transformation implemented in QEMU. Li et al [12] implemented vectorisation from x86 to Itanium architecture.…”

Section: Related Workmentioning

confidence: 99%

The janus triad: exploiting parallelism through dynamic binary modification

Zhou

Wort

Erdős

et al. 2019

Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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We present a uni ed approach for exploiting thread-level, data-level, and memory-level parallelism through a same-ISA dynamic binary modi er guided by static binary analysis. A static binary analyser rst examines an executable and determines the operations required to extract parallelism at runtime, encoding them as a series of rewrite rules that a dynamic binary modi er uses to perform binary transformation. We demonstrate this framework by exploiting three di erent kinds of parallelism to perform automatic vectorisation, software prefetching, and automatic parallelisation together on legacy application binaries. Software prefetch insertion alone achieves an average speedup of 1.2×, comparing favourably with an automatic compiler pass. Automatic vectorisation brings speedups of 2.7× on the TSVC benchmarks, signi cantly beating a compiler approach for some workloads. Finally, combining prefetching, vectorisation, and parallelisation realises a speedup of 3.8× on a representative application loop.

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“…Most efforts focus on redesigning algorithms to leverage SIMD instructions [17,31,34,36,72], exploring SIMD usage in new application domains [18,21,32,90], and improving SIMD code generation at the compiler level [7,27]. SIMD instructions have also been considered in dynamic binary translation (DBT) efforts [19,26,33,52,54,71], which focus on efficient translation of SIMD registers between ISAs. In addition to cross-ISA SIMD translations at migration points, our work also conducts SIMD-aware scheduling to maximize system throughput of workloads composed of SIMD and non-SIMD applications -entirely out of scope for DBT efforts.…”

Section: Related Workmentioning

confidence: 99%

Cross-ISA execution of SIMD regions for improved performance

Pang

Lyerly

Ravindran

2019

Proceedings of the 12th ACM International Conference on Systems and Storage

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We investigate the effectiveness of executing SIMD workloads on multiprocessors with heterogeneous Instruction Set Architecture (ISA) cores. Heterogeneous ISAs offer an intriguing clock speed/parallelism tradeoff for workloads with frequent usage of SIMD instructions. We consider dynamic migration of SIMD and non-SIMD workloads across ISA-different cores to exploit this trade-off. We present the necessary modifications for a general compiler/run-time infrastructure to transform the dynamic program state of SIMD regions at run-time from one ISA format to another for cross-ISA migration and execution. Additionally, we present a SIMD-aware scheduling policy that makes cross-ISA migration decisions that improve system throughput. We prototype a heterogeneous-ISA system using an Intel Xeon x86-64 server and a Cavium ThunderX ARMv8 server and evaluate the effectiveness of our infrastructure and scheduling policy. Our results reveal that cross-ISA execution migration within SIMD regions can yield throughput gains up to 36% compared to traditional homogeneous ISA systems.

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Exploiting Longer SIMD Lanes in Dynamic Binary Translation

Cited by 7 publications

References 8 publications

Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation

Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation

The janus triad: exploiting parallelism through dynamic binary modification

Cross-ISA execution of SIMD regions for improved performance

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