2011
DOI: 10.1109/jphot.2011.2140367
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Exploiting CMOS Manufacturing to Reduce Tuning Requirements for Resonant Optical Devices

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Cited by 137 publications
(63 citation statements)
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“…However, current system designs suggest that such large tuning ranges are unnecessary. Advances in silicon photonic fabrication have been able to control wafer and etch tolerances to produce relatively evenly spaced WDM microring arrays [74]. In evenly channel-spaced WDM microring arrays, no microring will need to be initially tuned beyond one channel spacing length.…”
Section: Resultsmentioning
confidence: 99%
“…However, current system designs suggest that such large tuning ranges are unnecessary. Advances in silicon photonic fabrication have been able to control wafer and etch tolerances to produce relatively evenly spaced WDM microring arrays [74]. In evenly channel-spaced WDM microring arrays, no microring will need to be initially tuned beyond one channel spacing length.…”
Section: Resultsmentioning
confidence: 99%
“…This is far from the 2015 energy target for tunable WDM filters of 30 fJ/bit [2] or reported values of 15 fJ/bit [11] using under-etched waveguides and flexible wavelength registration. Another way to improve the power consumption could come from (1) fabrication, where a better control over the silicon waveguide thickness could lower the maximum tuning range required [12], (2) from design, by using designs with larger FSR and thus increasing the wavelength shift for given power consumption or (3) by an increased bitrate.…”
Section: B Thermal Tuningmentioning
confidence: 83%
“…As no mode conversion and coupling occur in the PRS for the TE 0 mode input, the performance metrics remain stable with the above variation for the TE 0 mode input through our simulation. Manufacturing deviations with a top silicon thickness variation of AE5 nm and linewidth variations <1% are demonstrated in silicon photonic platforms [11,12] , which are smaller than the fabrication tolerances of the design. Due to the adiabatic conversion and coupling of modes in the bi-level taper and counter-tapered coupler, the width, thickness, or wavelength variation only lead to the position shift of the mode hybridizations and phase-matching points and will not affect the PRS performance seriously.…”
mentioning
confidence: 95%
“…The fabrication process sensitivity of the device is also analyzed, showing a large fabrication tolerance with a waveguide width variation of AE40 nm and top silicon thickness or slab height variation of AE10 nm for the entire operation waveband. Considering the manufacturing deviations in industrial silicon photonic foundries that have a top silicon thickness variation of AE5 nm and linewidth variations <1% [11,12] , this proposed device is quite fabrication tolerant. With such a broad operating bandwidth and a robust performance, this device offers great potential in silicon photonic systems, especially in applications requiring large bandwidths, such as WDM PONs for FTTH.…”
mentioning
confidence: 99%