Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis

Ruiz-Sautua, R.; Molina, M.C.; Mendias, J.M.

doi:10.1109/tcad.2007.895570

Cited by 4 publications

(1 citation statement)

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“…In this paper, a low power MPEG-1 motion vector reconstructor is designed using a behavioural synthesis methodology. Behavioural synthesis transforms an algorithmic or behavioural description of a design into a register transfer level (RTL) implementation [12]. The main tasks of behavioural synthesis are scheduling, allocation and binding.…”

Section: Introductionmentioning

confidence: 99%

Design of a low power MPEG-1 motion vector reconstructor

Ochoa-Montiel

Al-Hashimi

Kollig³

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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This paper describes the design of a low power MPEG-1 motion vector reconstructor using behavioural synthesis methodology. Various techniques, such as appropriate voltage scaling after clock and operations throughput selection, and reduction of multiplexer-based interconnection complexity are used to reduce power consumption. The design has been implemented based on a library components previously synthesised using Synplify ASIC w design has been performed through timing simulation with ModelSim, whereas power analysis is based on the reports obtained with PrimePower from Synopsys. The proposed design dissipates 42% less power than a power unaware design operated at the maximum supply voltage of the library components, i.e. 1.32V.

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Section: Introductionmentioning

confidence: 99%