A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier

Barrio, Alberto A. Del; Hermida, R.; Memik, Seda Öǧrenci

doi:10.1109/tc.2016.2529626

Cited by 10 publications

(4 citation statements)

References 36 publications

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“…These are set with parameters in the Register-Transfer Level (RTL) description of the core, so they take effect at synthesis time. Furthermore, as typically the multiplicative arithmetic units are among the most power-hungry modules [34], [35], [36], we permit either the use of the logarithm-approximate units presented in [37] or exact units for the multiplication, division and square root operations [38]. The exact units for these last two operations use a non-restoring division algorithm [39].…”

Section: Big-percival Corementioning

confidence: 99%

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Mallasén,

Del Barrio,

Prieto-Matias

2024

IEEE Trans. Comput.

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The accuracy requirements in many scientific computing workloads result in the use of double-precision floating-point arithmetic in the execution kernels. Nevertheless, emerging real-number representations, such as posit arithmetic, show promise in delivering even higher accuracy in such computations. In this work, we explore the native use of 64-bit posits in a series of numerical benchmarks and compare their timing performance, accuracy and hardware cost to IEEE 754 doubles. In addition, we also study the conjugate gradient method for numerically solving systems of linear equations in real-world applications. For this, we extend the PERCIVAL RISC-V core and the Xposit custom RISC-V extension with posit64 and quire operations. Results show that posit64 can obtain up to 4 orders of magnitude lower mean square error than doubles. This leads to a reduction in the number of iterations required for convergence in some iterative solvers. However, leveraging the quire accumulator register can limit the order of some operations such as matrix multiplications. Furthermore, detailed FPGA and ASIC synthesis results highlight the significant hardware cost of 64-bit posit arithmetic and quire. Despite this, the large accuracy improvements achieved with the same memory bandwidth suggest that posit arithmetic may provide a potential alternative representation for scientific computing.

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Section: Big-percival Corementioning

confidence: 99%

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Mallasén,

Del Barrio,

Prieto-Matias

2024

IEEE Trans. Comput.

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“…The design of a parallel counter ranging from 3:2 to 31:5 is demonstrated by Jones and Swartzlander [13]. Authors proposed on the fly multi‐speculative multiplier, which uses the partial carry‐save tree and booth encoding to reduce the depth of the multiplier structure [14] and radix‐8 based multiplier designed by Del Barrio et al. [15].…”

Section: Literature Reviewmentioning

confidence: 99%

Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

Krishna¹,

Neeharika

Janjirala³

et al. 2020

IET Computers & Digital Tech

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This paper proposes an efficient approach to design high-speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re-ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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“…CSA is a powerful architecture for fast multi-operand addition adder. CSAs are primarily used with array multipliers to build the process of accumulating the partial products [19][20][21][22][23]. The major goal of this work is to provide a fast, and area efficient modified implementation of the CSA.…”

Section: Introductionmentioning

confidence: 99%

High speed modified carry save adder using a structure of multiplexers

Hameed

Kathem

2021

IJECE

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Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.

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A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier

Cited by 10 publications

References 36 publications

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

High speed modified carry save adder using a structure of multiplexers

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