Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation

Liu, Yuping; Hong, Ding-Yong; Wu, Jan‐Jan; Fu, Sheng-Yu; Hsu, Wei-Chung

doi:10.1109/pact.2017.15

Cited by 10 publications

(4 citation statements)

References 31 publications

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“…In addition, there are several schemes proposed to optimize DBT systems [43,58,[65][66][67]77]. Basically, our HTM virtualization mechanism can cooperate with these optimizations to further improve the emulation performance.…”

Section: Related Workmentioning

confidence: 99%

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Wang

Yew

Zhai

et al. 2020

Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization

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System virtualization is a key enabling technology. However, existing virtualization techniques suffer from a significant limitation due to their limited cross-ISA support for emerging architecture-specific hardware extensions. To address this issue, we make the first attempt at hardware transactional memory (HTM), which has been supported by modern multi-core processors and used by more and more applications to simplify concurrent programming. In particular, we propose an efficient and scalable mechanism to support cross-ISA virtualization of HTMs. The mechanism emulates guest HTMs using host HTMs, and tries to preserve as much as possible the performance and the scalability of guest applications. Experimental results on STAMP benchmarks show that an average of 2.3X and 12.6X performance speedup can be achieved respectively for x86_64 and PowerPC64 guest applications on an x86_64 host machine. Moreover, it can attain similar scalability to the native execution of the applications. CCS Concepts• Software and its engineering → Justin-time compilers; Runtime environments; Dynamic compilers; Virtual machines; Multithreading; • Hardware → Emerging languages and compilers.

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Section: Related Workmentioning

confidence: 99%

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Wang

Yew

Zhai

et al. 2020

Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization

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“…Hong et al [11,13] proposed using a machine-independent IR layer to achieve cross-ISA SIMD transformation implemented in QEMU. Li et al [12] implemented vectorisation from x86 to Itanium architecture.…”

Section: Related Workmentioning

confidence: 99%

The janus triad: exploiting parallelism through dynamic binary modification

Zhou

Wort

Erdős

et al. 2019

Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

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We present a uni ed approach for exploiting thread-level, data-level, and memory-level parallelism through a same-ISA dynamic binary modi er guided by static binary analysis. A static binary analyser rst examines an executable and determines the operations required to extract parallelism at runtime, encoding them as a series of rewrite rules that a dynamic binary modi er uses to perform binary transformation. We demonstrate this framework by exploiting three di erent kinds of parallelism to perform automatic vectorisation, software prefetching, and automatic parallelisation together on legacy application binaries. Software prefetch insertion alone achieves an average speedup of 1.2×, comparing favourably with an automatic compiler pass. Automatic vectorisation brings speedups of 2.7× on the TSVC benchmarks, signi cantly beating a compiler approach for some workloads. Finally, combining prefetching, vectorisation, and parallelisation realises a speedup of 3.8× on a representative application loop.

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“…Most efforts focus on redesigning algorithms to leverage SIMD instructions [17,31,34,36,72], exploring SIMD usage in new application domains [18,21,32,90], and improving SIMD code generation at the compiler level [7,27]. SIMD instructions have also been considered in dynamic binary translation (DBT) efforts [19,26,33,52,54,71], which focus on efficient translation of SIMD registers between ISAs. In addition to cross-ISA SIMD translations at migration points, our work also conducts SIMD-aware scheduling to maximize system throughput of workloads composed of SIMD and non-SIMD applications -entirely out of scope for DBT efforts.…”

Section: Related Workmentioning

confidence: 99%

Cross-ISA execution of SIMD regions for improved performance

Pang

Lyerly

Ravindran

2019

Proceedings of the 12th ACM International Conference on Systems and Storage

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We investigate the effectiveness of executing SIMD workloads on multiprocessors with heterogeneous Instruction Set Architecture (ISA) cores. Heterogeneous ISAs offer an intriguing clock speed/parallelism tradeoff for workloads with frequent usage of SIMD instructions. We consider dynamic migration of SIMD and non-SIMD workloads across ISA-different cores to exploit this trade-off. We present the necessary modifications for a general compiler/run-time infrastructure to transform the dynamic program state of SIMD regions at run-time from one ISA format to another for cross-ISA migration and execution. Additionally, we present a SIMD-aware scheduling policy that makes cross-ISA migration decisions that improve system throughput. We prototype a heterogeneous-ISA system using an Intel Xeon x86-64 server and a Cavium ThunderX ARMv8 server and evaluate the effectiveness of our infrastructure and scheduling policy. Our results reveal that cross-ISA execution migration within SIMD regions can yield throughput gains up to 36% compared to traditional homogeneous ISA systems.

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Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation

Cited by 10 publications

References 31 publications

Efficient and scalable cross-ISA virtualization of hardware transactional memory

Efficient and scalable cross-ISA virtualization of hardware transactional memory

The janus triad: exploiting parallelism through dynamic binary modification

Cross-ISA execution of SIMD regions for improved performance

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