Expert system to configure global design for testability structure in a VLSI circuit

Bhawmik, Sudipta; Palchaudhuri, P.

doi:10.1016/0141-9331(89)90147-6

Cited by 7 publications

(1 citation statement)

References 5 publications

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“…Several approaches have been reported, varying from testability analysis [4,8,9,15] to testability method selecting [5,12,14,17,18,20,23]. A number of the proposed systems integrate DFT in a design in either a procedural fashion [3,10,21] or a knowledge-based one [1,2,6,7,11,13,16, 19,22].…”

Section: Motivation For Wagnermentioning

confidence: 99%

Integrating ASIC and board design-for-testability

Kraak

Proceedings Euro ASIC '92

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This paper presents the knowledge-based system WAG-NER that integrates the application of design-for-testability methods for boards, A S K S and boards containing ASICs. The system adapts the design to testing by using expert DFT knowledge and heuristics stored in a rulebase called TRISTAN and ISOLDE. T R I S m (TRI-Stage Testability ANalysis) qualitatively analyzes the testability of a circuit uniformly over the complete design hierarchy. It recognizes three design levels, i.e. the functional level, called block level, the RT or module level and the logic level. ISOLDE (Intelligent Synthesis Of testabLe DEsigns) synthesizes testability features on the basis of TRISTAN's analysis results at each design level, select-ing the most appropriate feature. A prototype implementation of the system in Prolog has been evaluated for several designs, showing the approach is feasible for automated testable design.

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Section: Motivation For Wagnermentioning

confidence: 99%

Integrating ASIC and board design-for-testability

Kraak

Proceedings Euro ASIC '92

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TIES: A testability increase expert system for VLSI design

1995

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TIES is a knowledge based system that advises the ICs designer on the best modifications to perform on a circuit with testability problems, while satisfying design constraints defined by the user. The proposed approach differs from previous papers for three main reasons. The DfT techniques are applied only to critical areas of the circuit which are identified by means of a testability measure. A powerful description of design for testability techniques in the knowledge base is adopted. Moreover, a new decision scheme for the comparison among different implementations is proposed

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