TIES: A testability increase expert system for VLSI design

Abstract

TIES is a knowledge based system that advises the ICs designer on the best modifications to perform on a circuit with testability problems, while satisfying design constraints defined by the user. The proposed approach differs from previous papers for three main reasons. The DfT techniques are applied only to critical areas of the circuit which are identified by means of a testability measure. A powerful description of design for testability techniques in the knowledge base is adopted. Moreover, a new decision scheme for the comparison among different implementations is proposed