Experimental study to push the Flash floating gate memories toward low energy applications

Marca, V. Della; Régnier, A.; Ogier, Jean-Luc; Simola, Roberto; Niel, S.; Postel-Pellerin, J.; Lalande, F.; Molas, G.

doi:10.1109/isdrs.2011.6135271

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Cited by 2 publications

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References 7 publications

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“…In this section we study the dependence between program pulse shape, biases, and the programming consumption of Si-nc memory cells. To this aim, the experimental setup described in [12] is used. The setup (figure 3) includes in particular an Agilent B1500 semiconductor device analyzer, equipped by two pulse generator modules WGFMU (Waveform Generator and Fast Measurement Unit).…”

Section: Resultsmentioning

confidence: 99%

Optimization of programming consumption of silicon nanocrystal memories for low power applications

Marca

Masoero

Molas

et al. 2012

2012 International Semiconductor Conference Dresden-Grenoble (ISCDG)

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In this paper we propose the optimization of the programming operation scheme of Silicon nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power applications. Using the program kinetic characteristics and a dynamic current measurement method, the programming window and the energy consumption during Channel Hot Electrons programming are deeply analyzed; evaluating ramp and box pulse with various gate and drain voltage biases. Finally the critical role of the tunnel oxide is evaluated to satisfy both retention and consumption requirements.

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Section: Resultsmentioning

confidence: 99%