Experimental Realization of a Nanomagnet Full Adder Using Slanted-Edge Magnets

Varga, Edit; Niemier, Michael; Csaba, G.; Bernstein, Gary H.; Porod, Wolfgang

doi:10.1109/tmag.2013.2249576

Cited by 54 publications

(20 citation statements)

References 15 publications

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“…By using our proposed five-input majority gate we are able to improve on the number of cells in the full adder design from [5] without requiring additional input copies such as in [7]. We wanted our designs to consist of uniform symmetric cells so other existing designs such as [3,4,8], and so on, were not considered in our comparisons. To our knowledge, there are no existing NML implementations of a full subtractor, therefore a full subtractor design in NML is also proposed in this Letter.…”

Section: Fig 1 Logic Values In Nml Computingmentioning

confidence: 99%

Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing

Labrado

Thapliyal

2016

Electron. lett.

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Section: Fig 1 Logic Values In Nml Computingmentioning

confidence: 99%

Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing

Labrado

Thapliyal

2016

Electron. lett.

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“…The same logic gate would be considered as an AND gate if opposite configuration for input and output state, i.e., logic 0 for upward (+y) state and logic 1 for downward (−y) state, is chosen [6].…”

Section: Geometry Of Integrated Structurementioning

confidence: 99%

“…The computation is performed through the fringing field interaction between the neighboring single-domain nanomagnets without direct charge flow, which makes it a low-power scheme compared with CMOS technology. Key elements of the NML library including logic gates [2], [3], interconnects [3], [4], fanout [5], and a 1 bit NML full adder [6] have already been demonstrated experimentally at room temperature using external clock field and nonprogrammable hard-coded inputs. A programmable input scheme [7] has been implemented, where inputs were set by changing the direction of the clock field.…”

Section: Introductionmentioning

confidence: 99%

Nanomagnet Logic Gate With Programmable-Electrical Input

et al. 2014

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We report a clock/logic/input structure for nanomagnet logic (NML) that implements a two-input slant-based OR gate with both clocking and input programming through current pulses. The clock line is a copper conductor embedded in a Si substrate with CoFe as a flux concentrator. Inputs are implemented with overlaid and dedicated bias lines. The programmability of such inputs allows us to test the same NML device for all possible input combinations. Results are determined by magnetic force microscopy. This scheme is easy to fabricate and can control thicker (20-30 nm) input nanomagnets. Close proximity of bias lines in such a structure allows us to investigate the effect of overlapping bias fields. We also report micromagnetic simulations that relate the slant in the output magnet to the dimensions of the input nanomagnets required to effect proper logic operation.Index Terms-Nanomagnet logic (NML), on-chip integration, programmable input.

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“…Consequently, numerous contributions to their physical realisation have been made in the past, e.g. atomic quantum cellular automata [10], nanomagnetic logic [11, 12] or molecular quantum cellular automata [13]. Thus, the components of electronic circuits such as wires, logic gates, full‐adders, among others can be implemented using the QCA architecture.…”

Section: Introductionmentioning

confidence: 99%

Gray‐code adder with parity generator – a novel quantum‐dot cellular automata implementation

Vieira

Neto

2020

IET Circuits, Devices & Systems

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This study describes the first Gray-code adder architecture, without the need to transform the Gray code into binary code, using the quantum-dot cellular automata (QCA). This device is a widely used resource for machine communications, counters, and encoders. QCA is a possible alternative to the current integrated circuit [complementary metal oxide semiconductor (CMOS)] due to its nanometric scale and very low-power consumption. In a bottom-up approach, the authors first describe and present the architecture of an important building block that composes the Gray-code adder, the parity generator, and then describe the full architecture. Besides being essential in the proposed adder, the parity generator is also important for error-checking and construction of other devices and widely used in communications. They demonstrate the functionality, test, and validate the proposed architectures using the QCADesigner simulator. If QCA consolidates as a possible CMOS substitute, this study can impact the design of future components that uses Gray-code and parity generator, such as embedded digital communications systems that will benefit from the low-power consumption of the QCA technology.

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Experimental Realization of a Nanomagnet Full Adder Using Slanted-Edge Magnets

Cited by 54 publications

References 15 publications

Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing

Design of a multilayer five‐input majority gate and adder/subtractor circuits in NML computing

Nanomagnet Logic Gate With Programmable-Electrical Input

Gray‐code adder with parity generator – a novel quantum‐dot cellular automata implementation

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