Experimental methodology for power characterization of FPGAs

Herrera-Alzu, I.; Sánchez, María del Carmen; López‐Vallejo, Marisa; Echeverría, Pedro

doi:10.1109/icecs.2008.4674920

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…The power valúes for interconnects are greater than their real valúes in order to compénsate for the increase in static power due to the higher temperature generated by the activity in large designs. Indeed, the results in [21] demónstrate that the XPower errors are below 30% for larger benchmarks implemented on the same platform. Consequently, it seems that low-level tools are suitable for coarse architecture optimization (order of watts), but they are not suitable for power model validation.…”

Section: Measurements Vs Low-level Estimationsmentioning

confidence: 84%

Power Measurement Methodology for FPGA Devices

Jevtić

Carreras

2011

IEEE Trans. Instrum. Meas.

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The efficiency of power optimization tools depends on information on design power provided by the power estimation models. Power models targeting different power groups can enable fast identification of the most power consuming parts of design and their properties. The accuracy of these estimation models is highly dependent on the accuracy of the method used for their characterization. The highest precisión is achieved by using physical on-board measurements. In this work, we present a measurement methodology that is primarily aimed at calibrating and validating high-level dynamic power estimation models. The measurements have been carefully designed to enable the separation of the interconnect power from the logic power and the power of the clock circuitry, so that each of these power groups can be used for the corresponding model validation. The standard measurement uncertainty is lower than 2% of the measured valué even with a very small number of repeated measurements. Additionally, the accuracy of a commercial low-level power estimation tool has been also assessed for comparison purposes. The results indícate that, the tool is not suitable for power estimation of data path oriented designs.

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Section: Measurements Vs Low-level Estimationsmentioning

confidence: 84%

Power Measurement Methodology for FPGA Devices

Jevtić

Carreras

2011

IEEE Trans. Instrum. Meas.

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“…El error de la estimación de consumo es mayor que en el caso de la estimación de área, debido a que por una parte utiliza la propia estimación de área y por otra parte obtiene los datos a partir de las herramientas de Xilinx, que aunque se realizan sobre diseños ya implementados se corresponden con una estimación. A pesar del error cometido, la estimación se obtiene de una manera rápida con la generación del propio core, y por lo tanto necesita muchos menos recursos y tiempo que la obtenida a partir de las herramientas de desarrollo o utilizando medidas experimentales [HASLVE08].…”

Section: Estimación De Consumounclassified

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

Marcos¹

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This PhD. thesis addresses the design and implementation of signal processing applications using reconfigurable FPGA platforms. This kind of platform exhibits high logic capability, incorporates dedicated signal processing elements and provides a low cost solution, which makes it ideal for the development of signal processing applications, where intensive data processing is required in order to obtain high performance.However, the cost associated to the hardware development on these platforms is high. While the increase in logic capacity of FPGA devices allows the development of complete systems, high-performance constraints require the optimization of operators at very low level. In addition to time constraints imposed by these applications, Area constraints are also applied related to the particular device, which force to evaluate and verify a design among different implementation alternatives. The design and implementation cycle for these applications can be tedious and long, being therefore normal that new FPGA models with a greater capacity and higher speed appear before completing the system implementation. Thus, the original constraints which guided the design of the system become useless.Different methods can be used to improve the productivity when developing these applications, and consequently shorten their design cycle. This PhD. Thesis focuses on the reuse of hardware components previously designed and verified. Although conventional HDLs allow the reuse of components already defined, their specification can be improved in order to simplify the process of incorporating new design components. Thus, a first part of the PhD. Thesis will focus on the specification of designs based on predefined components. This specification improves and simplifies the process of adding components to a description, but it also seeks to improve the quality of the design specified with better configuration options and even offering to report on features of the description.Hardware reuse of a component for its integration into a system largely depends on the information it offers. In this sense the conventional HDLs only provide together with the component description, the input/output interface and a set of parameters for its configuration, while other information is usually provided by external documentation. In the second part of the Thesis we will propose a formal way of encapsulation which aims to incorporate with the component description information that can be useful for its integration into other designs. This information will include features of the own implementation, but it will also support component configuration, and even information on how to configure and connect the component to carry out a function.Finally, the fast Fourier transform (FFT) will be chosen as a well-known signal processing application. It will be used as case study to illustrate the possibilities of porposed v specification and encapsulation formalisms. The objective of the FFT design is not only to show practical examples of the proposed s...

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Experimental methodology for power characterization of FPGAs

Cited by 2 publications

References 8 publications

Power Measurement Methodology for FPGA Devices

Power Measurement Methodology for FPGA Devices

Implementación de Algoritmos de Procesado de Señal sobre FPGA: Especificación, Reutilización y Exploración del Espacio de Diseño

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