Experimental evidence for voltage driven breakdown models in ultrathin gate oxides

Nicollian, P.E.; Hunter, W. R.; Hu, Jerry C.

doi:10.1109/relphy.2000.843884

Cited by 86 publications

(46 citation statements)

References 22 publications

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“…Therefore, correlates with the electron energy not the oxide field. This was also demonstrated for conventional Fowler-Nordheim stress by varying the doping of the anode [34], [95]. The SHE experiments also showed that is inversely related to the current density [93], again showing that breakdown is dominated by the effect of the energetic electrons and not the field in the oxide.…”

Section: Physical Models For Defect Generationmentioning

confidence: 55%

“…A recent modification of the AHI model [68], [69] proposes that a weaker minority carrier ionization process [70] is responsible for hole injection and defect generation at low voltages. This mechanism will be operative for electron injection into a p-type material or hole inversion layer, and was observed for n-FETs with low gate doping when the n-poly gate inverted [34]. The modified model can successfully fit the measured slope of -versus-voltage at high fields [67], [69] but cannot account for the absolute magnitude of the defect generation rate.…”

Section: Physical Models For Defect Generationmentioning

confidence: 99%

“…For breakdown, it is believed that bulk traps are the most important [31]- [34]. Eventually, enough damage builds up to the point where the oxide breaks down destructively.…”

Section: Introductionmentioning

confidence: 99%

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Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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Section: Physical Models For Defect Generationmentioning

confidence: 55%

Section: Physical Models For Defect Generationmentioning

confidence: 99%

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Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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“…Since the devices have the same threshold voltage, the effective stressing condition is the same for both groups of samples. Note that breakdown of thinner gate oxide occurs by bulk trap generation, not by interface trap generation, and is therefore driven by gate voltage [25]. With PCT Mo sputtering, the gate oxide integrity is significantly improved; indicating that low sputtering damage to gate dielectric is achieved.…”

Section: A Mo Sputter Depositionmentioning

confidence: 99%

Molybdenum Gate Technology for Ultrathin-Body MOSFETs and FinFETs

Takeuchi

Choi

et al. 2004

IEEE Trans. Electron Devices

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Abstract-Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully depleted silicon-on-insulator ( devices such as the ultrathin body (UTB) MOSFET and double-gate FinFET. A plasma charge trap effectively eliminates high-energy particle bombardment during Mo sputtering; hence the gate-dielectric integrity (TDDB, BD ) is significantly improved and the field-effect mobility in Mo-gated MOSFETs follows the universal mobility curve. The effects of etch process parameters such as chlorine (Cl 2 ) and oxygen (O 2 ) gas flow rate, and source and bias radio frequence powers, were investigated in order to optimize the Mo etch rate and selectivity to SiO 2 . A highly selective etch process was successfully applied to pattern Mo gate electrodes for UTB MOSFETs and FinFETs without leaving any residue or stringers. Measured electrical characteristics and physical analysis results are discussed.Index Terms-Complementary metal-oxide-semiconductor (CMOS), dry etching, FinFET, fully depleted silicon-on-insulator (FD SOI), molybdenum metal gate, sputter, ultrathin body.

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“…Nonetheless it was refuted by several authors [27]- [30]. A major endorsement of the power law model, however, came from the experimental work performed by Nicollian et al [31]. The latter showed that the time to breakdown did not reduce after decreasing the doping in the poly silicon gate.…”

Section: Introductionmentioning

confidence: 99%

Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress

Malobabic

Ellis

Salcedo

et al. 2008

2008 7th International Caribbean Conference on Devices, Circuits and Systems

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Abstract-Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using different pulserise times and -widths. The switching of oxide behavior pre-and post-breakdown occurs in tenths of a nanosecond and it shows reproducible voltage and current characteristics. The total stress and time-dependent-dielectric-breakdown (TDDB) during pulsed stress-method are evaluated using the following two procedures: 1) by adding up the total pulsed stress time, and 2) by extrapolation of the pulsed stress time to a constant voltage stress (CVS)-type measurements. It is shown that the latter method allows for a better comparison of identical oxides TDDB under various stress conditions. A methodology to characterize gate oxide breakdown using a single pulse is finally discussed. This is important to assess the gate-oxide failure condition during a charged device model (CDM)-type electrostatic discharge (ESD).

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Experimental evidence for voltage driven breakdown models in ultrathin gate oxides

Cited by 86 publications

References 22 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Molybdenum Gate Technology for Ultrathin-Body MOSFETs and FinFETs

Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress

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