Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers

Chindalore, G.; Hareland, S.A.; Jallepalli, S.; Tasch, A.F.; Maziar, C.M.; Chia, Victor K. F.; Smith, Stephen P.

doi:10.1109/55.568765

Cited by 71 publications

(24 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The lowering increases rapidly below a 50-nm effective channel length and reaches almost 0.1 V in a 30-nm MOSFET. This threshold voltage lowering will partially compensate the increase in the threshold voltage associated with quantum mechanical effects [25] in short, heavily doped MOSFET's, not taken into account in our simulations. No analytical models predicting the random dopant related threshold voltage lowering are available at present.…”

Section: B Channel Lengthmentioning

confidence: 94%

Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study

Asenov

1998

IEEE Trans. Electron Devices

593

315

View full text Add to dashboard Cite

show abstract

Section: B Channel Lengthmentioning

confidence: 94%

Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study

Asenov

1998

IEEE Trans. Electron Devices

593

315

View full text Add to dashboard Cite

show abstract

“…The confinement effects introduce a threshold voltage shift, simultaneously reducing the gate-to-channel capacitance and the charge in the channel available for transport [26], [27]. The reduced gate-to-channel capacitance also adversely affects the electrostatic integrity.…”

mentioning

confidence: 99%

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Wang

Al-Ameri

Wang

et al. 2015

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

show abstract

“…However, in such ultra-scaled GAA transistors, the quantum mechanical effects play a significant role and they must be considered in order to obtain accurate results about the device performance [6][7][8]. For example the quantum confinement effects lead to quantum threshold voltage shifts, simultaneously reducing the gate-to-channel capacitance and the available transport charge in the channel [9,10]. The reduced gate-to-channel capacitance also has a negative effect on the electrostatic integrity.…”

Section: Intoductionmentioning

confidence: 99%

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Al-Ameri

Wang

Georgiev

et al. 2015

2015 IEEE Nanotechnology Materials and Devices Conference (NMDC)

View full text Add to dashboard Cite

Abstract-This work investigates the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six various cross-section shapes. However all devices in the crosssectional area is kept constant in order to provide fair comparison between them. Additionally we expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we were able to obtain correlation between the mobile charge distributions in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs is also investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such nano-scale dimensions.

show abstract

Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers

Cited by 71 publications

References 10 publications

Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study

Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

Contact Info

Product

Resources

About