Experimental Detection and Numerical Validation of Different Failure Mechanisms in IGBTs During Unclamped Inductive Switching

Abstract

The physics of the different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in punchthrough (PT) and not PT (NPT) insulated-gate bipolar transistor (IGBT) structures is analyzed in this paper. Both 3-D electrothermal numerical simulations and experimental evaluations support the theoretical analysis. Experimental results for UIS test show that, at low time duration (or inductance value) of the test, the UIS limit moves from energy limitation to current limitation. While the energy limitation is well known, the current-limited failures are less studied. In this paper, the current limit for UIS test is analyzed in detail, and the cause is attributed to a filamentary current conduction due to the presence of a negative differential resistance (NDR) region in the $I_{C}$– $V_{rm CE}$ curve in breakdown. The filamentary current conduction locally increases the current density causing early device latch-up and possible device failure at a current much lower than the one dictated by energy limitations. The physical parameters that affect both the onset of NDR region and the failure current are discussed for both an NPT trench IGBT structure with a local lifetime control and a PT trench IGBT structure with a field-stop layer

Short-circuit robustness of SiC Power MOSFETs: Experimental analysis

“…Robust design of SiC based power systems requires detailed analysis of the device performance in a number of abnormal operational conditions (i.e., non-intentional and typically out of SOA, but not necessarily infrequent), such as short-circuit, over-current/over-temperature turn-off, unclamped inductive switching [1][2][3]. This paper focuses on the in-depth characterization of the transistors during Short-Circuit (SC) operation.…”

Novel Cathode Design to Improve the ESD Capability of 600 V Fast Recovery Epitaxial Diodes

“…It is known that ESD current is sustained by carriers generated by impact ionization and in this condition electrical behavior related to the presence of a Negative Differential Resistance (NDR) can arise. As it has been demonstrated in [3][4][5][6][7][8] the presence of a NDR branch in the blocking I-V curve can lead to current filamentation and possible early failure of the device. Optical investigations have highlighted damages coherent with current filamentation (Figure 1).…”

Investigation and Classification of Short-Circuit Failure Modes Based on Three-Dimensional Safe Operating Area for High-Power IGBT Modules

“…More specifically, one is the static current filament which will directly drive the device into thermal runaway [41]. In contrast, the other one is the hopping current filament, of which the latch up of the corresponding cells is more likely to be triggered as a subsequent failure mechanism [42]. As for the factors that influence the forms of the current filament, both the layout of the chip level and gate drive voltage are of great importance [43][44].…”