Experimental demonstration of standby power reduction using voltage stacking in an 8Kb embedded FDSOI SRAM

Abstract

Voltage stacking has been proposed as an efficient solution for power delivery in high performance processors, for 3D ICs, for pin-limited ICs, and for implicit sleep mode (standby) DC/DC conversion. In this paper we demonstrate voltage stacking for an 8Kb embedded SRAM in 180nm fully-depleted SOI (FDSOI) which leads to 88.6% reduction in standby power, including overhead.The SRAM is formed of two 4Kb subarrayswhich are powered in parallel during active mode, and stacked in series during standby. The SRAM uses no explicit decoupling or regulating and achieves active-to-sleep and sleep-to-active transitions of less than 10ns and a breakeven time of 20ns.

Breaking the power delivery wall using voltage stacking

“…In [1] the authors used voltage stacking for 3D integrated circuits. In [3] the authors demonstrated the effectiveness of stacking scheme in saving standby power in SRAM by 88.6%. In [4] the authors have used voltage stacking to Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

“…Similar solutions have been proposed earlier for 3D ICs, for pin limited ICs, for implicit high efficient DC-DC conversion, reduction of standby power in SRAM and power supply noise suppression [1][2][3][4].…”