Breaking the power delivery wall using voltage stacking

Mazumdar, Kaushik; Stan, Mircea R.

doi:10.1145/2206781.2206795

Cited by 13 publications

(17 citation statements)

References 7 publications

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“…In response to the power delivery challenge caused by excessive current consumption, various research proposals [1][2][3][4] explored the idea of using a charge-recycled power delivery structure to support 3D-IC. Charge-recycling, or voltage-stacking (V-S), refers to power delivery that ar ranges multiple circuit blocks electrically in series.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, explicit voltage regulation is required in V-S PDNs to compensate for the current-consumption mismatch between layers, and regulate voltages at the in ternal nodes. Based on circuit-level implementations and tests, prior research proposals have demonstrated the fea sibility of using these explicit regulators in V-S PDNs [2,4]. However, the trade-off in voltage noise between V-S PDNs and traditional PDNs is not clear.…”

Section: Introductionmentioning

confidence: 99%

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Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Zhang

Mazumdar

Meyer

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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Ahstract-Aside from the benefits it brings, 3D-IC technology inevitably exacerbates the difficulty of power delivery with volumetrically increasing power consumption. Recent work managed to "recycle" current within the 3D stack by linking the different layers' supply/ground nets into a series connection. This charge-recycled (also known as voltage-stacked, or V-S) scheme provides a scalable so lution for 3D-IC's power delivery because it supports an arbitrary number of layers with a constant off-chip current demand. Although prior work has studied the circuit im plementation of a V-S power delivery network (PDN) and its current-reduction benefits, a whole-system evaluation of V-S PDNs' transient voltage noise and a noise comparison between the V-S PDN and the traditional PDN are miss ing. In this paper, we build a system-level model to exam ine voltage-stacked 3D-ICs' transient noise and explore the impact of different PDN design parameters and workload behaviors. Our results show that compared with the tra ditional PDN scheme, V-S provides stronger isolation for cross-layer noise interference, which in turn grants higher performance benefits for run-time noise mitigation tech niques, such as dynamic margin adaptation. We observe that, compared with traditional PDNs, V-S PDNs provide up to 60% lower transient noise in the worst-case scenario. Furthermore, we show that V-S PDNs significantly reduce the packaging cost, because their noise is almost insensitive to the package impedance (e.g., a 300% impedance increase only raises worst-case noise by less than 0.3% Vdd).

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Zhang

Mazumdar

Meyer

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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“…With this internal recycling, for almost the same power consumption, the current drawn through the supply will be reduced to 1/n of conventional parallel loads (n is the number of cores stacked) [5][6][7]. This will also reduce the off-chip I 2 R power loss by a factor of n 2 and IR drop by a factor of n. The efficiency of this technique depends on the current mismatch among the stacked domains.…”

Section: Voltage Stacking Ideamentioning

confidence: 99%

“…By using a SC regulator, the achievable efficiency can be more than LDO. This idea is an extension of our work on GALS-based stacked cores which allow the intermediate node to implicitly track the workload of the different cores [5].…”

Section: Dc-dc Conversion Using Voltage Stackingmentioning

confidence: 99%

“…Thus the benefits of wide range DVFS are negated by the lack of efficient conversion techniques. This bottleneck has been referred to as the on-chip power regulation efficiency wall (where the relatively poor efficiencies achievable with on-chip regulators limit the effectiveness of many low power schemes that depend on on-chip regulation) [5].…”

Section: Introductionmentioning

confidence: 99%

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Exploration of Charge Recycling DC-DC Conversion Using a Switched Capacitor Regulator

Mazumdar

Stan

2013

JLPEA

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Abstract:The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. The idea is to supply nominal (high) off-chip voltage to the cores which are then "voltage-stacked" to generate the near-threshold (low) voltages based on Kirchhoff's voltage law through charge recycling. However, the effectiveness of this implicit down-conversion is affected by the current imbalance among the cores. The paper presents a design methodology and optimization strategy for highly efficient charge recycling on-chip regulation using a push-pull switched capacitor (SC) circuit. A dual-boundary hysteretic feedback control circuit has been designed for stacked loads. A stacked-voltage domain with its self-regulation capability combined with a SC converter has shown average efficiency of 78%-93% for 2:1 down-conversion with ILoad (max) of 200 mA and workload imbalance varying from 0-100%.

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On hyperbolic laws of capacitor discharge through self‐timed digital loads

Yakovlev

Kushnerov

Mokhov

et al. 2014

Circuit Theory & Apps

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SUMMARYA new model to predict the dynamic behavior of a self-timed autonomous digital system powered by a capacitor is derived. The model demonstrates the hyperbolic shape of the discharging process on the capacitor. It allows a symbolic analysis of the discharging process for complex digital loads comprised of series (stack) and parallel configurations of digital circuits. For example, for a stack configuration, important non-trivial relationships between the hyperbolic discharging rates have been derived based on the knowledge of the velocity saturation index (alpha) of the semiconductor devices used in the digital part. For a realistic (modern complementary metal oxide semiconductor (CMOS) devices) value of alpha = 1.5, the discharging process for a stack of two identical circuits proceeds nearly three times slower than that of any of the stand-alone circuits. This shows a potential way of extending the lifetime of the energy sources by means of stacking self-timed circuits. Although the analysis is based on configurations consisting of ring oscillators in CMOS technology, the analysis method can be extended to other types of self-timed systems and other semiconductor technologies in which the instantaneous switching activity of the digital load is determined by the instantaneous voltage levels provided by the capacitive power transfer mechanism. The analytical derivations have been validated by simulations and experiments carried out with real hardware.

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Breaking the power delivery wall using voltage stacking

Cited by 13 publications

References 7 publications

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC

Exploration of Charge Recycling DC-DC Conversion Using a Switched Capacitor Regulator

On hyperbolic laws of capacitor discharge through self‐timed digital loads

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