Experimental Characterization of CMOS Interconnect Open Defects

Arumí, D.; Rodríguez-Montañés, R.; Figueras, Joan

doi:10.1109/tcad.2007.907255

Cited by 56 publications

(28 citation statements)

References 28 publications

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“…If the nets and nodes are at Logic-0, they reduce the victim net voltage. This model has been verified by measurements on manufactured designs [121,82] and by its ability to predict open defect locations [72]. The amount of charge that can be trapped on a victim net due to a full open is not well known, but Q trapped /C victim to GN D has been assumed to correspond to a variation of [−0.3V, 0.3V ] in [122] and a variation of [−1V, 1V ] in [80] and in [123] the trapped charge has been assumed negligible taking into account the possibility to eliminate this charge during IC fabrication.…”

Section: Capacitive Coupling Modelmentioning

confidence: 77%

“…Another study [129] recommends an N-detection approach using are well controllable [122]. That is why three studies, [82,127,126], recommend controlling the neighbour nets to Logic-1 in order to test for Stuck-At-1 type behaviour and to Logic-0 in order to test for Stuck-At-0 type behaviour. The fact that neighbouring nets influence the circuit behaviour at the fault site can be understood by considering the capacitive coupling between nets that are physically close to one another as will be reviewed in Section 4.2.…”

Section: Test Methods For Full Open Defectsmentioning

confidence: 99%

“…If the neighbouring node is down-stream from the victim net, i.e. if the logic value on the neighbouring node depends on the voltage on the victim net, it forms a feedback loop, with the possibility of oscillation or memory effects [125,97,82,122].…”

Section: Capacitive Coupling Modelmentioning

confidence: 99%

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Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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The final part studies the impact of process variation on the behaviour of bridge defects.Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation.

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Section: Capacitive Coupling Modelmentioning

confidence: 77%

Section: Test Methods For Full Open Defectsmentioning

confidence: 99%

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Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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“…In a general configuration with multiple neighbors, the state of the entire neighborhood should be considered to determine fault detectability, as already considered for interconnect full open faults [24], [27], [28]. The problem is similar to that about crosstalk in [29] and [30], but with more relaxed conditions.…”

Section: Test Recommendationsmentioning

confidence: 99%

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

2016

IEEE Trans. VLSI Syst.

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Abstract-Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

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“…Hard opens, especially the open gate defect, due to the complete disconnection of the line strongly depends on the technology and physical topology of the circuit and are more difficult to model in an initial stage of the circuit analysis [12].…”

Section: Fig 4 Catastrophic Transistor Fault Modelmentioning

confidence: 99%

Test Based on Built-In Current Sensors for Mixed-Signal Circuits

Mozuelos

Lechuga

Martínez

et al. 2010

IFIP Advances in Information and Communication Technology

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Abstract. This paper presents a test methodology for mixed-signal circuits. The test approach uses a built-in sensor to analyze the dynamic current supply of the circuit under test. This current sensor emphasizes the highest harmonics of the dynamic current of the circuit under test when the current to voltage conversion is done. The goodness of the test method is analyzed first by means of a fault simulation and afterwards through the experimental data obtained from several benchmark circuits.

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Experimental Characterization of CMOS Interconnect Open Defects

Cited by 56 publications

References 28 publications

Investigation into voltage and process variation-aware manufacturing test

Investigation into voltage and process variation-aware manufacturing test

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Test Based on Built-In Current Sensors for Mixed-Signal Circuits

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