Experimental Assessment of Electrons and Holes in Erase Transient of TANOS and TANVaS Memories

Suhane, A.; Arreghini, A.; bosch, G. Van den; Vandelli, Luca; Padovani, Andrea; Breuil, L.; Larcher, Luca; Meyer, K. De; Houdt, J. Van

doi:10.1109/led.2010.2055824

Cited by 13 publications

(12 citation statements)

References 8 publications

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“…damages due to electrons coming from the trapping layer or the gate and reaching the substrate with high energy [11]. In our case, both TANOS and THANOS devices are operating in a regime where hole injection dominates over electron de-trapping ( [1]). Therefore, the degradation from electron, is limited as electron injection from the gate is still not present at this point.…”

Section: Resultsmentioning

confidence: 95%

“…Hence, we do not observe any effect of HfO 2 capping on THANOS endurance. For devices where VariOT is used as tunnel dielectric layer, the erase is initially governed by hole injection from the substrate, and followed by the saturation due to electron injection from the gate [1]. THANVaS device operates far from saturation (see Fig.…”

Section: Resultsmentioning

confidence: 99%

“…Moreover, for MLC operation in Solid State Drives (SSD) these memories will also require excellent endurance along with large memory window. Various solutions have been proposed, such as engineered tunnel oxide [1]- [4] and blocking dielectric [5]; however achieving large memory window (>8 V) without sacrificing endurance and retention is still problematic.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper we fabricate a Hafnium Oxide (HfO 2 ) capping layer on top of the Al 2 O 3 blocking oxide in TANOS and TANVaS [1] memories, resulting in THANOS and THANVaS devices, respectively. We benchmark these devices against reference in order to understand their impact on memory performance through electrical evaluation.…”

Section: Introductionmentioning

confidence: 99%

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High Performance THANVaS Memories for MLC Charge Trap NAND Flash

Suhane

bosch

Arreghini

et al. 2011

2011 3rd IEEE International Memory Workshop (IMW)

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In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO2 capping layer on top of the Al2O3 blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TANOS with variable tunnel oxide thickness (TANVaS), respectively. It is found that HfO2 capping layer improves erase saturation level due to its better electron blocking capabilities during erase operation, as also confirmed by simulations. As a result of improved erase saturation, THANVaS device shows excellent performance of 9.5 V memory window with flat endurance up to 10 4 cycles and improved high temperature retention.

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Section: Resultsmentioning

confidence: 95%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High Performance THANVaS Memories for MLC Charge Trap NAND Flash

Suhane

bosch

Arreghini

et al. 2011

2011 3rd IEEE International Memory Workshop (IMW)

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“…As the composition of the SiN layer becomes less Si-rich, the erase mechanism shifts from electron detrapping toward hole injection (7). It is also recognized that the SiO 2 /SiN/SiO 2 (ONO) tunnel structure enhances hole injection during erase operation (7)(8)(9). Since the amount of interface states, shown in Fig.2, clearly increases with increasing hole fluence during erasing, it is concluded that the interface-state generation is mainly due to holes injected during erasing.…”

Section: Interface-state Generation By Program/erase Stressmentioning

confidence: 99%

(Invited) Defect Generation Mechanism and Its Impact on Reliability Properties in MONOS Devices

Fujii¹,

Kusai²,

Sakuma³

et al. 2014

ECS Trans.

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The interface-state generation mechanism and its impact on reliability properties, such as endurance and data retention, in MONOS devices have been studied. The charge measurement technique we developed has demonstrated that holes injected during erasing are the main cause of interface-state generation. From carrier separation measurement for MONOS devices, we have found the data retention degradation after P/E stress is owing to the increased hole injection from Si substrate via the generated interface states. We also discuss the physical origin of the interface states in MONOS devices and report on MONOS-specific interface-state generation/recovery phenomena, and their significant impact on endurance and retention properties. IntroductionThe metal-oxide-nitride-oxide-semiconductor (MONOS) device is a focus of attention owing to its potential as a future nonvolatile memory device (1, 2). For the use of MONOS devices, it is important to understand accurately the mechanism of reliability degradation induced by electrical stress such as programming and erasing (P/E). In this paper, we report on the mechanism of defect generation by P/E stress and its impact on reliability properties, such as endurance and data retention characteristics, in MONOS devices. Firstly, we clarify the mechanism of interface-state generation in MONOS devices under P/E stress. We demonstrate, using a charge measurement technique we developed, that interface-state generation, which is the origin of window instability, has a strong correlation with the amount of charges flowing into MONOS during erasing, and that holes injected from Si substrate are the main cause of endurance degradation.

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