Experimental and theoretical characterization of submicron MOSFETs

Fichtner, W.; Fuls, E.N.; Johnston, R.L.; Sheng, T. T.; Watts, R. O.

doi:10.1109/iedm.1980.189743

Cited by 18 publications

(5 citation statements)

References 7 publications

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“…The CVD oxide and 250A of the t h e r m a l l y grown SiO2 were RIE anisotropically in CHF3/NH,~. The additional etching of t h e r m a l l y grown oxide simulates the etching of 250A thick first gate oxide which is a typical gate oxide thickness in submicron channel devices (26). The samples were then oxidized in dry T2/HC1 ambient at 1000~ for 16 min to simulate the growth of 250A second gate oxide.…”

Section: Methodsmentioning

confidence: 99%

Oxide Isolation for Double‐Polysilicon VLSI Devices

Levin¹,

Sheng²

1983

J. Electrochem. Soc.

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A novel method for the formation of an isolation layer between the polysilicon layers in double‐polysilicon VLSI devices is described. The intermediate oxide is realized by means of CVD oxide or a combination of polyoxide on top of the first polysilicon layer and CVD oxide on its walls. The isolation can be applied also to structures having a first conductor level which is difficult to oxidize. Test capacitors indicate that very low freak population, lowleakage currents, and breakdown voltages higher than 50V between the polysilicon layers can be achieved by the use of the method. The results are compared to double‐polysilicon structures having thermally grown sidewall oxide.

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Section: Methodsmentioning

confidence: 99%

Oxide Isolation for Double‐Polysilicon VLSI Devices

Levin¹,

Sheng²

1983

J. Electrochem. Soc.

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“…(1)(2)(3) Performance gain due to the shrinkage of transistors' size has promoted the use of submicron channel length transistors in practical applications. However, there are several difficulties in the design of processing sequences of such devices to be compatible with conventional production-line processes.…”

Section: Introductionmentioning

confidence: 99%

An optimally designed process for submicron MOSFETs

Shibata

Hieda²,

Sato³

et al. 1981

1981 International Electron Devices Meeting

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An n-channel MOS process has been optimized to yield desirable characteristics for submicron channel length MOSFETs. Process/device simulation is extensively used to find an optimized processing sequence compatible to typical production line processes. The simulation results show an excellent agreement to experimental data.We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5V, and minimized substrate bias effects for transistors with channel lengths as small as 0 . 5~. The short channel effects have been also minimized. A unique self-aligned silicidation technology which has been developed to reduce the increased resistance of down-scaled junctions is also presented.

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“…To this end, numerical simulation programs (2) have been developed to allow accurate device modelling, and a radically ne\? : semiconductor lithographic technology based on the use of 4.36A X-rays has been implemented.…”

Section: Introductionmentioning

confidence: 99%

Scaling the micron barrier with x-rays

Lepselter¹

1980

1980 International Electron Devices Meeting

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INTRODUCTIONA dramatic increase in device performance results from fabricating properly-designed MOSFETs with submicron channel lengths (1). As a direct result of these short channels subnanosecond circuits become practical, and further increase the inexorable pressure towards ever-finer features.The challenge, as well as opportunity, has been to develop the necessary tools to successfully allow fabrication and design of this new breed of devices. To this end, numerical simulation programs (2) have been developed to allow accurate device modelling, and a radically ne\?: semiconductor lithographic technology based on the use of 4.36A X-rays has been implemented.The exposure tool, the X-ray mask, and the X-ray resist will be described. SCALINGAs the technological process steps become more complicated and thus more expensive, the numerical simulation of the problems arising from short-channel design for MOS devids has emerged as a very elegant way to solve some of the main problems. This simulation must not be restricted to the device itself but has to include a more or less accurate description of the process steps themselves, if the interrelation between processing and device behavior is to be successfully modelled. Simulation packages have been developed which allow a first-principle computer modelling of process steps and device behavior in one and two dimensions in a routine way: a. Modelling of implantation, predeposition and annealing steps in one and two dimensions.b. Modelling of MOS device performance in two dimensions.As MOSFET dimensions are reduced, it is desirable to preserve long-channel behavior. In general, lower voltages, shallower junctions, thinner oxides and heavier doping help to maintain longchannel behavior as channel length is reduced. We have proposed a generalized guide for MOSFET miniaturization at the IEDM 1979 (3) which provides a simple estimate for MOSFET parameters, not requiring reduction of all dimensions by the same scale.As a representative example, Fig. 1 shows the Z D / V~ characteristics for an MOS device with LcR = 0.4 pm.At higher drain voltages, this device is limited in performance by velocity saturation of the electrons in the channel. The sourcedrain breakdown of this device occurs at V , = 5.2V for V,, = OV. l D / V , characteristics for 0.4 p m transistor: oxide thickness 230A junction depth 0.25 p m channel doping X-RAY LITHOGRAPHY The Exposure SystemThe rudiments of an X-ray proximity printer are illustrated in Fig. 2 (4). A 4 kilowatt electron beam is focused onto a stationary, water-cooled palladium cone-target, which in turn emits X-rays at a characteristic wavelength of 4.36A. Cooling is done by the nucleate boiling of high-velocity water flowing across the outside of the palladium cone ( 5 ) .The resist-coated sample is held on a chuck in a helium filled chamber, at atmospheric pressure. The X-rays pass through a beryllium window and expose the un-masked resist, passing along a straight line emanating from the focused spot 50 cm away. (6) The X-Ray Mask

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Experimental and theoretical characterization of submicron MOSFETs

Cited by 18 publications

References 7 publications

Oxide Isolation for Double‐Polysilicon VLSI Devices

Oxide Isolation for Double‐Polysilicon VLSI Devices

An optimally designed process for submicron MOSFETs

Scaling the micron barrier with x-rays

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