Experimental and modeling study of the capacitance–voltage characteristics of metal–insulator–semiconductor capacitor based on pentacene/parylene

Wondmagegn, Wudyalew; Satyala, Nikhil; Mejía, I.; Mao, Duo; Gowrisanker, S.; Alshareef, Husam N.; Stiegler, H.; Quevedo‐Lopez, Manuel; Pieper, R.J.; Gnade, Bruce E.

doi:10.1016/j.tsf.2011.02.014

Cited by 16 publications

(7 citation statements)

References 51 publications

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“…For V ohm = 0.42 V and d = 160 nm, a density of carriers was found in the order of 4 × 10 16 cm −3 , which is in good agreement with data reported in [28] and [29]. Finally, the mobility was determined from the experimental characteristic in zone IV and presented in the following equation:…”

Section: Resultssupporting

confidence: 86%

Electrical Study of Pentacene-Based Metal–Semiconductor–Metal Structure: Schottky Barrier and Active Layer Thickness Effects

Khaldi

Boubaker

Nasri

et al. 2018

IEEE Trans. Electron Devices

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The impact of electrodes and active layer thickness on the current-voltage characteristics of Au/Pentacene/Al structure was studied using a physicallybased 2-D simulation by solving Poisson's, continuity, and drift diffusion equations. The main parameters required for simulation are extracted from the logarithmic representation of experimental current-voltage curves. The simulation results produce an excellent overlapping with the experimental data after including parameters previously found in our model. Finally, the simulation was used to better understand the physical processes together with mechanisms governing the efficiency of the device under investigation and to have a predictive behavior.

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Section: Resultssupporting

confidence: 86%

Electrical Study of Pentacene-Based Metal–Semiconductor–Metal Structure: Schottky Barrier and Active Layer Thickness Effects

Khaldi

Boubaker

Nasri

et al. 2018

IEEE Trans. Electron Devices

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“…We focus our efforts to extract the DOS width and we accomplish this by numerical fitting of experimental measurements, exploiting the fact that the DOS width has a sizable impact on the spatial distribution of accumulated carriers, which in turn affects the shape of the CV curve. Apart from few exceptions [47,48], the correlation between the dependence of the MIS capacitance on the gate bias and the DOS width has been overlooked, and CV measurements on organic MIS structures have been analyzed in the framework of Mott-Schottky depletion region [49][50][51] or have been used to extract the contact resistance at the metal/semiconductor interface [52,53].…”

Section: Introductionmentioning

confidence: 99%

Assessing the width of Gaussian density of states in organic semiconductors

Maddalena

Falco

Caironi

et al. 2015

Organic Electronics

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“…Also, a negligible hysteresis is observed, as the C-V curve-shift ∆V of 150 mV is very small [22,23]. An MIS capacitor is generally modeled as two capacitors in series: the insulator capacitance C i and the semiconductor-depletion-layer capacitance C s [21,22,24]; hence, the capacitance…”

Section: Capacitance-voltage Characterization Before Application Of C...mentioning

confidence: 99%

Charge Buildup and Leakage Current in Gold/Parylene-C/ Pentacene Capacitor under Constant-Voltage Stress

Khawaji

Brigeman

Awadelkarim

et al. 2020

Flex. Print. Electron.

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Degradation of metal-insulator-semiconductor (MIS) capacitors of gold/Parylene-C/Pentacene under constant voltage stress (CVS) was investigated to explore the electrical stability and reliability of Parylene C as a gate dielectric in flexible electronics. A stress voltage of fixed magnitude as high as 20 V, both negative and positive in polarity, was applied to each MIS capacitor at room temperature for a fixed duration as long as 10 s. The CVS effects on the capacitance-voltage curve-shift, the time-dependent leakage current and the time-dependent dielectric breakdown were measured and analyzed. CVS is observed to induce charge in Parylene-C and its interfaces with gold and Pentacene. The net induced charge is positive and negative for, respectively, negative and positive gate bias polarity during CVS. The magnitude of the charge accumulated following positive gate CVS is significantly higher than that following negative gate bias CVS in the range of 4 to 25 nC cm −2 . In contrast, the leakage current during the negative gate stress is three orders of magnitude higher than that during the positive gate stress for the same bias stress magnitude. The charge buildup and leakage current are due to the trapping of electrons and holes near the Parylene-C/Pentacene interface as well as in the Parylene-C layer.Before the application of the CVS, a dielectric breakdown occurs at an electric field of 1.62 MV cm −1 . After the application of the CVS, the breakdown voltage decreases and the density of the trapped charges increases as the stress voltage increases in magnitude, with the polarity of the trapped charges opposite to that of the stress voltage. The magnitude and direction of the capacitance-voltage curve-shift depend on the trapping and recombination of electrons and holes in the Parylene-C layer and in the proximity of the Parylene-C/Pentacene interface during CVS.

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Experimental and modeling study of the capacitance–voltage characteristics of metal–insulator–semiconductor capacitor based on pentacene/parylene

Cited by 16 publications

References 51 publications

Electrical Study of Pentacene-Based Metal–Semiconductor–Metal Structure: Schottky Barrier and Active Layer Thickness Effects

Electrical Study of Pentacene-Based Metal–Semiconductor–Metal Structure: Schottky Barrier and Active Layer Thickness Effects

Assessing the width of Gaussian density of states in organic semiconductors

Charge Buildup and Leakage Current in Gold/Parylene-C/ Pentacene Capacitor under Constant-Voltage Stress

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